• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.190.1-190
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• 2000

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.39-39
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• 2000

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• Journal of the Korean Ceramic Society
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• v.37 no.11
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• pp.1051-1057
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• 2000

TiO$_2$와 CeO$_2$박막을 Si 위에 증착한 후 MOCVD법에 의해 PbTiO$_3$박막을 증착하여 MFIS 구조를 형성하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해 산소분위기와 $600^{\circ}C$~90$0^{\circ}C$의 온도범위에서 후 열처리를 행하였고, C-V 특성 및 누설전류 특성을 분석하였다. CeO$_2$와 TiO$_2$박막의 유전상수는 증착 직후 6.9와 15였으며, 90$0^{\circ}C$ 열처리를 행한 후 약 4.9와 8.8로 감소하였다. 누설전류밀도 역시 증착 직후 각각 7$\times$$10^{-5}$ A/$ extrm{cm}^2$와 2.5$\times$$10^{-5}$ A/$\textrm{cm}^2$에서 90$0^{\circ}C$ 열처리를 거친 후에 약 4$\times$$10^{-8}$ A/$\textrm{cm}^2$와 4$\times$$10^{-9}$ A/$\textrm{cm}^2$로 감소하였다. Ellipsometry 시뮬레이션을 통해 계산된 계면층의 두께는 90$0^{\circ}C$에서 약 115$\AA$(CeO$_2$) 및 140$\AA$(TiO$_2$)까지 증가하였다. 계면층은 MFIS 구조에서 강유전층에 인가되는 전계를 감소시켜 항전계를 증가시켰고, charge injection을 방지하여 Al/PbTiO$_3$/CeO$_2$(90$0^{\circ}C$, $O_2$)/Si 구조의 경우 $\pm$2 V~$\pm$10 V의 측정범위에서 memory window가 계속 증가하는 것을 보여주었다.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.377-385
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• 2002

The possibility of $ZrO_2$ thin film as insulator for Metal-Ferroelectric-Insulator-Semiconductor(MFIS) structure was investgated. $SrBi_2Ta_2O_9$ and $SrBi_2Ta_2O_9$(SBT) thin films were deposited on P-type Si(111) wafer by R. F. magnetron sputtering method. The electrical properties of MFIS gate were relatively improved by inserting the $ZrO_2$ buffer layer. The window memory increased from 0.5 to 2.2V in the applied gate voltage range of 3-9V when the thickness of SBT film increased from 160 to 220nm with 20nm thick $ZrO_2$. The maximum value of window memory is 2.2V in Pt/SBT(160nm)/$ZrO_2$(20nm)/Si structure with the optimum thickness of $ZrO_2$. These memory windows are sufficient for practical application of NDRO-FRAM operating at low voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• 전자공학회논문지 IE
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• v.43 no.2
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• pp.7-10
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• 2006

A GaN-based metal-insulator-semiconductor (MIS) structure has been fabricated by using $BaTa_2O_6$ instead of conventional oxide as insulator gate. The leakage current o) films are in order of $10^{-12}-10^{-13}A/cm^2$ for GaN on $Al_2O_3$(0001) substrate and in order of $10^{-6}-10^{-7}A/cm^2$ for GaN on GaAs(001) substrate. The leakage current of thses films is governed by space-charge-limited current over 45 MV/cm in case of GaN on $Al_2O_3$(0001) substrate and by Poole-Frenkel emission in case of GaN on GaAs(001).

• Journal of the Korean Chemical Society
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• v.40 no.3
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• pp.167-172
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• 1996

For the preparation of single-crystalline GaN film, heteroepitaxial growth on a sapphire substrate was carried out by halide vapor phase epitaxy(HVPE) method. The resulting GaN films showed n-type conductivity. The insulator type GaN film was made by doping with Zn(acceptor dopant), which showed emission peaks around 2.64 and 2.43 eV. The result of this study indicates that GaN can be obtained in an epitaxial structure of MIS(metal-insulator-semiconductor) junction. The observed data are regarded as fundamental in developing GaN epitaxial films for light emitting devices of hetero-structure type.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.388-388
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• 2013

현대 사회에서 고집적 및 고성능의 전자소자의 필요성은 지속적으로 요구되고 있으며, 투명하거나 플렉서블한 특성의 필요성에 따라 이에 대한 기술개발이 이루어지고 있다. 특히, 이러한 특성을 만족하면서 대면적화 및 저온 공정의 특성을 지니는 유기물 반도체가 주목받고 있고, 이를 이용하여 OLED (Organic Light Emitting Diode), OTFT (Organic Thin Film Transistor)와 같은 다양한 유기물 반도체 소자가 개발되고 있다. 대표적인 예로는이 있다. 유기물 반도체 소자의 특성을 이용한 메모리 소자 또한 연구 및 개발이 지속되고 있으며, 유연성과 낮은 공정가격 등의 특성을 가지는 나노 입자들이 기존 Floating Gate의 대체물로 각광받고 있다. 본 논문에서는 MIS (Metal/Insulator/Semiconductor) 구조를 제작하고, Insulator 내부에Core/Shell 구조를 가지는 CdSe/ZnS 나노 입자를 부착하여 메모리 소자의 특성 확인 및 단위 면적당 개수에 따른 특성 변화를 확인하고자 하였다. 합성된 PVP (Poly 4-Vinyl Phenol)를 Insulator 층으로 사용하였으며 단위 면적당 나노 입자의 개수를 조절하여 제작된 MIS 소자를 Capacitance versus Voltage (C-V) 측정을 통하여 변화특성을 확인하였다.