• 센서학회지
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• 제17권1호
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• pp.35-40
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• 2008

Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

• 센서학회지
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• 제21권1호
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권4호
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• pp.208-212
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• 2004

In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

• 센서학회지
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• 제17권5호
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• pp.346-349
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• 2008

A metal-semiconductor-metal (MSM) ultraviolet (UV) photodetector (PD) is proposed as an effective UV sensing device for integration with a GaN n-channel MISFET on auto-doped p-type GaN grown on a silicon substrate. Due to the high hole barrier of the metal-p-GaN contact, the dark current density of the fabricated MSM PD was less than $3\;nA/cm^2$ at a bias of up to 5 V. Meanwhile, the UV/visible rejection ratio was 400 and the cutoff wavelength of the spectral responsivity was 365 nm. However, the UV/visible ratio was limited by the sub-bandgap response, which was attributed to defectrelated deep traps in the p-GaN layer of the MSM PD. In conclusion, an MSM PD has a high process compatibility with the n-channel GaN Schottky barrier MISFET fabrication process and epitaxy on a silicon substrate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• 한국표면공학회지
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• 제47권1호
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• pp.20-24
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• 2014

Joule heat is generated by applying an electric filed to a conductive layer located beneath or above the amorphous silicon film, and is used to raise the temperature of the silicon film to crystallization temperature. An electric field was applied to an indium tin oxide (ITO) conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced within the range of a millisecond. To investigate the kinetics of Joule-heating induced crystallization (JIC) solid phase crystallization was conducted using amorphous silicon films deposited by plasma enhanced chemical vapor deposition and using tube furnace in nitrogen ambient. Microscopic and macroscopic uniformity of crystallinity of JIC poly-Si was measured to have better uniformity compared to that of poly-Si produced by other methods such as metal induced crystallization and Excimer laser crystallization.

• 한국산업보건학회지
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• 제26권2호
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• pp.119-138
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• 2016

Objectives: The purpose of this study is to review size, shape, and crystal structure-dependent toxicity of major metal oxide particles such as silicon dioxide, tungsten trioxide, aluminum oxide, and titanium dioxide as byproducts generated in semiconductor fabrication facility. Methods: To review the toxicity of major metal oxide particles, we used various reported research and review papers. The papers were searched by using websites such as Google Scholar and PubMed. Keyword search terms included '$SiO_2$(or $WO_3$ or $Al_2O_3$ or $TiO_2$) toxicity', 'health effects $SiO_2$(or $WO_3$ or $Al_2O_3$ or $TiO_2$). Additional papers were identified in references cited in the searched papers. Results: In various cell lines and organs of human and animals, cytotoxicity, genotoxicity, hepatoxicity, fetotoxicity, neurotoxicity, and histopathological changes were induced by silicon dioxide, tungsten trioxide, aluminium oxide, and titanium dioxide particles. Differences in toxicity were dependent on the cell lines, organs, doses, as well as the chemical composition, size, surface area, shape, and crystal structure of the particles. However, the doses used in the reported papers were higher than the possible exposure level in general work environment. Oxidative stress induced by the metal oxide particles plays a significant role in the expression of toxicity. Conclusions: The results cannot guarantee human toxicity of the metal oxide particles, because there is still a lack of available information about health effects on humans. In addition, toxicological studies under the exposure conditions in the actual work environment are needed.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.111.2-111.2
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• 2011

야금학적 방법을 통한 태양전지용 실리콘 제조를 위하여 아크로(Arc furnace)에서 제조된 용융 상태의 금속급 실리콘을 슬래그와 직접 반응시켜 불순물을 제거하는 공정에 관한 연구를 수행하였다. 이를 위해 아크로와 고주파 유도용해로(High-frequency induction furnace)를 이용하여 금속급 실리콘을 제조와 정련 특성 실험을 수행하였다. 본 연구에서 금속급 실리콘을 제조하기 위한 장비로 150kW급-DC 아크로와 300kW급-AC 아크로를 사용하였다. 원재료로 규석, 코크스(Cokes), 숯, 그리고 우드칩(Wood chip)을 실험 비율에 맞춰 아크로 내부에 장입하고, 이를 용융환원 방법을 통해 반응을 시켰다. 이때 생산된 금속급 실리콘의 순도는 약 99.2~99.8% 이었으며, 원재료의 순도, 장입 비율 및 아크로 운전 특성에 따라 편차가 있다. 아크로에서 생산된 금속급 실리콘의 경우 인(phosphorus), 붕소(boron)를 다량 함유하고 있고, 이를 제거하기 위하여 50kW급 고주파 유도용해로 장비를 사용하여 슬래그 정련 실험을 수행하였다. 슬래그 정련시 사용한 성분은 SiO2, CaO 그리고 CaF2 이며, 금속급 실리콘과 슬래그의 질량비 및 반응 시간에 따른 실리콘 불순물 특성을 평가하였다. 실험결과 인과 붕소는 각각 1 ppm 이하, 5 ppm 이하 였으며, 칼슘을 제외한 대부분의 금속 불순물의 경우 0.1~0.2% 임을 확인하였다.