• 한국수소및신에너지학회논문집
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• 제15권4호
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• pp.317-323
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• 2004

We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• 센서학회지
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• 제6권3호
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• pp.221-227
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• 1997

Pd/NiCr 게이트 MISFET 센서는 변압기 절연유중 용존수소를 감지하기 위해 제조되었다. 센서의 안정성과 고농도 감지성의 향상을 위해 Pd/NiCr 2중 촉매 금속 게이트가 사용되었다. 수소유입에 의한 게이트 전압의 드리프트를 줄이기 위해, 2개의 FET 게이트 절연층을 실리콘 산화막과 실리콘 질화막의 2중 구조로 하였다. Pd/NiCr 게이트 MISFET 센서의 수소 감응 감도는 Pd/Pt 게이트 MISFET 센서의 감도에 비해 약 0.5배이나, 안정성이 좋고, 1000 ppm까지의 고농도까지 측정할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.187-187
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• 2012

Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• 전기전자학회논문지
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• 제22권2호
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• 센서학회지
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• 제29권2호
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.