• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.2
• /
• pp.101-109
• /
• 1998

In this paper, we implemented holographic optical memory systm which can store and reconstruct many images using new input and angular multiplexing method. In the new input method, phase infomation of input image is inputed in the recording material instead of brightness information. To do so, we represented the images, which captured with CCD camera or displayed on the computer monitor, on the liquid crystal television(LCTV) which removed polarizer/analyzer. Therefore, we can generate uniform input beam intensity regardless of the total brightness of input image, and apply the scheduled recording method. Also we can increase the intensity of input beam so reduce the recording time of input image. And reconstructedimage is acquired by transforming phase information into brightness information of image with analyzer. The incident angle of reference beam is acquired by Fourier transform of the binary phase hologram(BPH) which designed with SA algorithm on the LCTV. The proposed optical memory system is stable because the incident angle of the reference beam is controlled easy and electronically. We demonstreated optical experiment which store and reconstruct various type images in BaTiO$_{3}$ using proposed holographic memory system.

• Journal of Oriental Neuropsychiatry
• /
• v.9 no.2
• /
• pp.37-44
• /
• 1998

Purpose: This study was conducted to find out the effects od Sahyangsohapwon on learning and memory of rats.Method: In the experiment, rats were divided two groups. One was control group which was adminstered Sahyangsohapwon and the other was sample group administered placebo. Numbers of each group were 13 rats. 8-arm radial maze task was used in it, and working memory test and retention(reference memory) test were done.Before the beginning of the test, the rats were deprived of water for 24hrs.In the frist test, each of eight arm was baited with water and a rat was permitted to remain on the maze until all eight arms were entered. A working memory error was defined as revisit of any previously entered arm. When a rat made an error not exceeding one time in consecutive 3 days-performance, it was regarded as learning criteria and the test was ended. The reference memory was evaluated with total days which it took rats to pass the learning crtirtia.The second test was performed after 24 hours when the first test was over. When a rat entered 4 arms, the entrance of arm was cut off during 30 seconds.Here the number if errors which was produced during a rat find remaining 4 tracks was regarded as the index of memory.This experiment compared the number of error at the control group with that of the sample group.Result: 1. In the first test, it was shown that the sample group took 7.69${\pm}$1.11 days and the control group 9.31${\pm}$1.97 days to pass the learning criteria.There was statistically significant reference mernory development at the sample group.2. In the second test, the frequency of errors made by the two groups were 0.92${\pm}$1.32 times for the control group and 1.23${\pm}$1.59 times for the Sahyangsohapwon group. There was no difference between the groups in frequency of errors.Conclusion: It is suggested that Sahyangsohapwon has effects on the improvement of learning and memory.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.6
• /
• pp.742-750
• /
• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Korea Society of Computer and Information
• /
• v.20 no.11
• /
• pp.1-8
• /
• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1555-1557
• /
• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.4
• /
• pp.86-91
• /
• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.4
• /
• pp.26-33
• /
• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.129-131
• /
• 2011

An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.12
• /
• pp.75-82
• /
• 1998

Many multiplexing techniques are proposed for high storage densities in a volume hologram. In this paper, we present a hybrid angularly and spatially multiplexed volume holographic memory system. Multiple holograms are recorded by using reference and object waves with different incident angles and positions that are changed by step motors. A hologram is written by exposing the crystal with recording time schedule to the interference pattern of the object beam and a reference plane wave. Finally, we show experimental results of the storage of three layers of 300 multiplexed holograms in a LiNbO$_3$ : Fe crystal.

• The Journal of the Acoustical Society of Korea
• /
• v.3 no.2
• /
• pp.13-22
• /
• 1984

A surface acoustic wave signal processing device using the silicon surface state is presented and shown capable of storing a reference signal and later correlating another signal with the stored reference. The device memory consists of the storage of the spatial 2k pattern of an acoustic wave as stored charges in the surface state of silicon surface. Results of experiments are presented which characterize the operation of device. Simpliied models for charging process and nonlinear acoustoelectric interactions based on consideration of single surface state at the surface of silicon The validity of simplified model has been qualitatibely confirmed with experimental results and the application of this device to aprogrammable matched filter of communication is considered.