• 전자공학회논문지D
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• 제35D권2호
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• pp.101-109
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• 1998

In this paper, we implemented holographic optical memory systm which can store and reconstruct many images using new input and angular multiplexing method. In the new input method, phase infomation of input image is inputed in the recording material instead of brightness information. To do so, we represented the images, which captured with CCD camera or displayed on the computer monitor, on the liquid crystal television(LCTV) which removed polarizer/analyzer. Therefore, we can generate uniform input beam intensity regardless of the total brightness of input image, and apply the scheduled recording method. Also we can increase the intensity of input beam so reduce the recording time of input image. And reconstructedimage is acquired by transforming phase information into brightness information of image with analyzer. The incident angle of reference beam is acquired by Fourier transform of the binary phase hologram(BPH) which designed with SA algorithm on the LCTV. The proposed optical memory system is stable because the incident angle of the reference beam is controlled easy and electronically. We demonstreated optical experiment which store and reconstruct various type images in BaTiO$_{3}$ using proposed holographic memory system.

• 동의신경정신과학회지
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• 제9권2호
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• pp.37-44
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• 1998

Purpose: This study was conducted to find out the effects od Sahyangsohapwon on learning and memory of rats.Method: In the experiment, rats were divided two groups. One was control group which was adminstered Sahyangsohapwon and the other was sample group administered placebo. Numbers of each group were 13 rats. 8-arm radial maze task was used in it, and working memory test and retention(reference memory) test were done.Before the beginning of the test, the rats were deprived of water for 24hrs.In the frist test, each of eight arm was baited with water and a rat was permitted to remain on the maze until all eight arms were entered. A working memory error was defined as revisit of any previously entered arm. When a rat made an error not exceeding one time in consecutive 3 days-performance, it was regarded as learning criteria and the test was ended. The reference memory was evaluated with total days which it took rats to pass the learning crtirtia.The second test was performed after 24 hours when the first test was over. When a rat entered 4 arms, the entrance of arm was cut off during 30 seconds.Here the number if errors which was produced during a rat find remaining 4 tracks was regarded as the index of memory.This experiment compared the number of error at the control group with that of the sample group.Result: 1. In the first test, it was shown that the sample group took 7.69${\pm}$1.11 days and the control group 9.31${\pm}$1.97 days to pass the learning criteria.There was statistically significant reference mernory development at the sample group.2. In the second test, the frequency of errors made by the two groups were 0.92${\pm}$1.32 times for the control group and 1.23${\pm}$1.59 times for the Sahyangsohapwon group. There was no difference between the groups in frequency of errors.Conclusion: It is suggested that Sahyangsohapwon has effects on the improvement of learning and memory.

• 한국정보전자통신기술학회논문지
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• 제11권6호
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• pp.742-750
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• 2018

본 논문에서는 $0.13{\mu}m$ BCD 공정 기반에서 5V MOS 소자만 사용하여 zero layer FTP 셀이 가능하도록 하기 위해 tunnel oxide 두께를 기존의 $82{\AA}$에서 5V MOS 소자의 gate oxide 두께인 $125{\AA}$을 그대로 사용하였고, 기존의 DNW은 BCD 공정에서 default로 사용하는 HDNW layer를 사용하였다. 그래서 제안된 zero layer FTP 셀은 tunnel oxide와 DNW 마스크의 추가가 필요 없도록 하였다. 그리고 메모리 IP 설계 관점에서는 designer memory 영역과 user memory 영역으로 나누는 dual memory 구조 대신 PMIC 칩의 아날로그 회로의 트리밍에만 사용하는 single memory 구조를 사용하였다. 또한 BGR(Bandgap Reference Voltage) 발생회로의 start-up 회로는 1.8V~5.5V의 전압 영역에서 동작하도록 설계하였다. 한편 64비트 FTP 메모리 IP가 power-on 되면 internal reset 신호에 의해 initial read data를 00H를 유지하도록 설계하였다. $0.13{\mu}m$ Magnachip 반도체 BCD 공정을 이용하여 설계된 64비트 FTP IP의 레이아웃 사이즈는 $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$)이다.

• 한국컴퓨터정보학회논문지
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• 제20권11호
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• 대한전자공학회논문지SD
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• 제49권4호
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• pp.26-33
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• 2012

임베디드 시스템의 저장매체 시장에서 플래시 메모리가 점유율을 높여나가고 시스템 내에서 대부분의 면적을 차지하게 되면서, 시스템 신뢰도에 무거운 영향을 미치고 있다. 플래시 메모 리는 셀 배열구조에 따라 NOR/NAND-형으로 나뉘어져 있고 플로팅 게이트 셀의 Reference 전압의 갯수 따라 SLC(Single Level Cell)와 MLC(Multi Level Cell)로 구분된다. NAND-형 플래시 메모리는 NOR-형에 비해 속도는 느린 편이지만 대용량화가 쉽고 가격이 저렴하다. 또한 MLC NAND-형 플래시 메모리는 대용량 메모리의 수요가 급격히 높아진 모바일 시장의 영향으로 멀티미디어 데이터 저장의 목적으로 널리 채용되고 있다. 이에 따라 MLC NAND-형 플래시 메모리의 신뢰성을 보장하기 위해 고장 검출 테스팅의 중요도 커지고 있다. 전통적인 RAM에서부터 SLC 플래시 메모리를 위한 테스팅 알고리즘은 많은 연구가 있었고 많은 고장을 검출해 내었다. 하지만 MLC 플래시 메모리의 경우 고장검출을 위한 테스팅 시도가 많지 않았기 때문에 본 논문은 SLC NAND-형 플래시 메모리에서 제안된 기법을 확장한 MLC NAND-형 플래시 메모리를 위한 고장검출 알고리즘을 제안하여 이러한 차이를 줄이려는 시도이다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.129-131
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• 2011

Hight speed memory application을 위하여 6.4-Gb/s/channel 4-PAM transceiver가 제안된다. Voltage margin과 time margin용 증가시키기 위하여 asymmetric 4-PAM scheme과 이를 위한 회로를 제안한다. 제안된 asymmetric 4-PAM scheme은 기존 회로에 비하여 송신단에서 33%의 기준전압 노이즈 영향을 줄인다. Channel의 ISI를 줄이기 위해서 transmitter의 1-tap pre-emphasis가 사용된다. 제안된 asymmetric 4-PAM transceiver는 1.2V supply 0.13um 1-poly 6-metal CMOS 공정에서 구현되었다. PLL을 포함한 1-channel transceiver의 면적과 전력소모는 각각 $0.294um^2$와 6mW이다.

• 전자공학회논문지D
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• 제35D권12호
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• pp.75-82
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• 1998

체적홀로그램의 저장용량을 향상시키기 위해서 여러 가지 다중화 기법이 제안되고 있는 가운데, 본 논문에서는 각다중화와 공간다중화를 병행한 복합 다중화 시스템을 구현하였다. 기준파의 각도 및 공간상의 위치를 변화시키는 방법으로 스텝 모터를 사용하여 다중 홀로그램을 기록할 수 있었다. 기록 시간 스케줄에 의하여 노출 시간을 조절하므로써 기준파와 물체파 간의 간섭 패턴을 홀로그램에 기록하였다. 3층 300개의 영상을 한 개의 LiNbO₃ :Fe에 기록하였으며 실험 결과를 보였다.

• 한국음향학회지
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• 제3권2호
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• pp.13-22
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• 1984

A surface acoustic wave signal processing device using the silicon surface state is presented and shown capable of storing a reference signal and later correlating another signal with the stored reference. The device memory consists of the storage of the spatial 2k pattern of an acoustic wave as stored charges in the surface state of silicon surface. Results of experiments are presented which characterize the operation of device. Simpliied models for charging process and nonlinear acoustoelectric interactions based on consideration of single surface state at the surface of silicon The validity of simplified model has been qualitatibely confirmed with experimental results and the application of this device to aprogrammable matched filter of communication is considered.