• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.531-536
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• 2021

As artificial intelligence technology advances, it is being applied to various application fields. Artificial intelligence is performing well in the field of image recognition and classification. Chip design specialized in this field is also actively being studied. Artificial intelligence-specific chips are designed to provide optimal performance for the applications. At the design task, memory component optimization is becoming an important issue. In this study, the optimal algorithm for the memory size exploration is presented, and the optimal memory size is becoming as a important factor in providing a proper design that meets the requirements of performance, cost, and power consumption.

• Journal of the Korean Home Economics Association
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• v.25 no.1
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• pp.121-127
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• 1987

The purpose of this study was to investigate the importance of mental capacity and to see whether it can be a barometer to predict childrne's cognitive development. The instruments used were Pictoral Test of Intelligence to select homogeneous samples, Cucui Scale for their M-power and Conservation Test. The results showed that M-power develops as age increases, and it can be a strong variable to predict their cognitive development. It has been demonstrated that capacity increases developmentally but whether this reflects changes in capacity perse, or in the efficient use of that capacity is a debatable issue. More study needs to be repeated for this matter.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.377-384
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

• Structural Engineering and Mechanics
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• v.82 no.1
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• pp.107-120
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• 2022

The bracing members capable of active control against seismic loads to reduce earthquake damage have been widely utilized in construction projects. Effectively reducing the structural damage caused by earthquake events, bracing systems equipped with retrofitting damper devices, which take advantage of the energy dissipation and impact absorption, have been widely used in practical construction sites. Shape Memory Alloys (SMAs) are a new generation of smart materials with the capability of recovering their predefined shape after experiencing a large strain. This is mainly due to the shape memory effects and the superelasticity of SMA. These properties make SMA an excellent alternative to be used in passive, semi-active, and active control systems in civil engineering applications. In this research, a new system in diagonal braces with slit damper combined with SMA is investigated. The diagonal element under the effect of tensile and compressive force turns to shear force in the slit damper and creates tension in the SMA. Therefore, by creating shear forces in the damper, it leads to yield and increases the energy absorption capacity of the system. The purpose of using SMA, in addition to increasing the stiffness and strength of the system, is to create reversibility for the system. According to the results, the highest capacity is related to the case where the ratio of the width of the middle section to the width of the end section (b₁/b) is 1.0 and the ratio of the height of the middle part to the total height of the damper (h₁/h) is 0.1. This is mainly because in this case, the damper section has the highest cross-section. In contrast, the lowest capacity is related to the case where b₁/b=0.1 and the ratio h₁/h=0.8.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.36-45
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• 2002

This paper introduces the design and implementation of a flash memory simulator to emulate a real flash memory. Since this simulator provides exact execution time information and parameter testing functions as well as the type, total capacity, block size, and page size of flash memory, it can be used as a real flash memory as viewed by the operating system. Furthermore, the simulator provides time logging functions of the internal routines of the flash memory management software allowing the monitoring of bottlenecks within the software. Finally, we show the performance measurements of applications under the Linux operating systems on both the simulator and a test board verifying the simulator's use as a replacement for real flash memory.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.405-412
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• 2002

The embedded system has less fast CPU and lower memory than PC(personal Computer) or Workstation system. Therefore embedded operating is system is designed to efficiently use the limited resource in the system. Virtual memory management or the embedded linux have a low efficiency when page fault is occurred to get a data from I/O device. Because a data is moving from the swap device to main memory. This paper suggests virtual memory compression algorithm for improving in virtual memory management and capacity of space. In this paper, we present a way to performance implement a virtual memory compression system that achieves significant improvement for the embedded system.

• Earthquakes and Structures
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• v.23 no.3
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• pp.221-229
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• 2022

The external post-tension technique is one of the best strengthening methods for reinforcement and improvement of the various steel structures and substructure components such as beams. In the present work, the load carrying capacity of the post-tensioned tapered steel beams with external shape memory alloy (SMA) tendons are studied. 3D nonlinear finite element method with ABAQUS software is used to determine the effects of the increase in the flexural strength, and the improvement of the load carrying capacity. The effect of the different parameters, such as geometrical characteristics and the post-tension force applied to the tendons are also studied in this research. The results reveal that the external post-tension with SMA tendons in comparison with the steel tendons causes a significant improvement of the loading capacity. According to this, using SMA tendon for the reinforcement of the tapered beams causes a decrease in weight of these structures and as a consequence causes economic benefits for their application. This method can be used extensively for steel beams due to low executive costs and simplicity of the operation for post-tension.