Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

Reallocation Data Reusing Technique for BISR of Embedded Memory Using Flash Memory

플래시 메모리를 이용한 내장 메모리 자가 복구의 재배치 데이타 사용 기술

  • 심은성 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학부)
  • Published : 2007.08.15
Download PDF
⟨ Previous Next ⟩

Abstract

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

최근 VLSI 회로 직접도가 급속도로 증가함에 따라 하나의 시스템 칩에 고밀도와 고용량의 내장 메모리가 구현되고 있다. 고장난 메모리를 여분의 메모리로 재배치함으로써 메모리 수율 향상과 사용자에게 메모리를 투명하게 사용할 수 있도록 제공할 수 있다. 본 논문에서는 고장난 메모리 부분을 여분의 행과 열 메모리로 효율적인 재배치를 위해 재배치 알고리즘을 제안하고자 한다. 재배치 정보는 고장난 메모리를 매번 테스트해야만 얻을 수 있다. 매번 테스트를 통해 재배치 정보를 얻는 것은 시간적 문제가 발생한다. 이것을 막기 위해 한번 테스트해서 얻은 재배치 정보를 플래시 메모리에 저장해 해결할 수 있다. 본 논문에서는 플래시 메모리를 이용해 재배치 정보의 활용도를 높인다.

Keywords

References

  1. Allan A., Edenfeld D., Joyner W.H. Jr., Kahng A.B., Rodgers M., and Zorian, Y., '2001 technology roadmap for semiconductors,' Computer, vol. 35, pp. 42-53, January 2002 https://doi.org/10.1109/MC.2002.993770
  2. Jone W.B., Huang D.C., Wu S.C., and Lee K.J., 'An efficient BIST method for distributed small buffers,' IEEE Transactions on Very Large Scale Integration Systems, vol. 10, pp. 512-515, August 2002 https://doi.org/10.1109/TVLSI.2002.800532
  3. Hamdioui S., and van de Goor A.J., 'Thorough testing of any multiport memory with linear tests,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 217-231, February 2002 https://doi.org/10.1109/43.980260
  4. Horiguchi M., Etoh J., Aoki M., Itoh K., and Matsumoto T., 'A flexible redundancy technique for high-density DRAMs,' IEEE Journal of Solid-State Circuits, vol. 26, pp. 12-17, January 1991 https://doi.org/10.1109/4.65704
  5. Ilyoung Kim, Zorian Y., Komoriya G., Pham H., Higgins F.P., and Lewandowski J.L., 'Built in self repair for embedded high density SRAM,' Proceedings of International Test Conference, pp. 1112-1119, 18-23 October 1998
  6. Heon Cheol Kim, Dong Soon Yi, Jin Young Park, and Chang Hyun Cho, 'A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies,' International Conference on VLSI and CAD, pp. 602-605, 26-27 October 1999
  7. Sy Yen Kuo, and Fuchs W.K., 'Efficient Spare Allocation in Reconfigurable Arrays,' Conference on Design Automation, pp. 385-390, 29-2 June 1986
  8. Chin Long Wey, and Lombardi F., 'On the Repair of Redundant RAM's,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 222-231, March 1987 https://doi.org/10.1109/TCAD.1987.1270266
  9. Wei Kang Huang, Yi Nan Shen, and Lombardi F., 'New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement,' IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 9, pp. 323-328, March 1990 https://doi.org/10.1109/43.46807
  10. Shyue Kung Lu, Yu Chen Tsai, Hsu C. H., Kuo Hua Wang, and Cheng Wen Wu, 'Efficient builtin redundancy analysis for embedded memories with 2-D redundancy,' IEEE Transactions on Very Large Scale Integration Systems, vol. 14, pp. 34-42, January 2006 https://doi.org/10.1109/TVLSI.2005.863189
  11. V. Schober, S. Paul, and O. Picot, 'Memory Built-In Self-Repair using redundant words,' Proceedings of International Test Conference, 2001
  12. R. Dean Adams, 'High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test,' Kluwer Academic Publishers, 2003