• Journal of Adhesion and Interface
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• v.24 no.4
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• pp.120-123
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• 2023

Graphene, with its exceptional mechanical and electrical properties, has gained significant attention from researchers due to its superior characteristics compared to conventional materials. However, the application of graphene in electronic devices requires a crucial transcription and patterning process, which often introduces numerous defects, substantially impairing its properties. To overcome this limitation and unlock the full potential of graphene for commercial use, there have been various efforts to develop integrated processes for transcription and patterning. In this study, we present a novel growth method that simultaneously achieves precise patterning using polymer nanowires as masks, allowing for the direct growth of graphene. This innovative approach holds promise for realizing advanced electronic components based on nanomaterials in the future.

• Journal of the Korean Physical Society
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• v.73 no.10
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• pp.1473-1478
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• 2018

In this study, we have developed a simple and cost-effective method to prevent edge bead formation by covering the edge of a chip-level substrate with heat-resistant tape during patterning using SU-8. Edge beads are a fundamental problem in photoresists and are particularly notable in high-viscosity fluids and thick coatings. Edge beads can give rise to an air gap between the substrate and the patterning mask during UV exposure, which results in non-uniform patterns. Furthermore, the sample may break since the edge bead is in contact with the mask. In particular, the SU-8 coating thickness of the chip-level substrates used in MEMS or BioMEMS may not be properly controlled because of the presence of edge beads. The proposed method to solve the edge bead problem can be easily and economically utilized without the need for a special device or chemicals. This method is simple and prevents edge bead formation on the sample substrate. Despite the small loss in the taping area, the uniformity of the SU-8 coating is improved from 50.9% to 5.6%.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.770-772
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• 2002

A new dry-processing method of organic gate dielectric film in field-effect transistors (FETs) was proposed. The method use vapor deposition polymerization (VDP) that is continuous and low temperature process. It has the advantages of shadow mask patterning and dry processing in flexible low-cost large area applications. Here, 80 nm-thick Al as a gate electrode was evaporated through shadow mask. Gate insulators used two different polyimides. The one material was 4,4'-oxydiphtahlic anhydride (ODPA) and 4,4'-oxydianiline (ODA). Another was 2,2-bis(3,4-dicarboxyphenyl) Hexafluoropropane Dianhydride (6FDA) and 4,4' -oxydianiline (ODA). These were co-deposited by high-vaccum thermal-evapora and cured at 150 $^{\circ}C$ for 1 hour, respectively. Pentacene as a semiconductor and 100 nm-thick Au as a source and drain electrode were evaporated through shadow mask.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.364-365
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• 2006

One of the promising routes for producing highly ordered nanostructures is a template method using the porous alumina membrane (PAM). Because the PAM is mechanically, chemically, thermally stabile with highly ordered structure, many researchers have studied under various experimental conditions to fabricate nanostructures. We present the information on the fabrication of about 300 nm nano-mask which have important applications for various patterned nanostructures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.11
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• pp.1135-1140
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• 2012

Two-step metallization processes have been proposed to achieve high-efficiency silicon solar cells, where the front-side grids are formed by silver plating after the formation of a nickel seed layer with a mask. Because the conventional mask patterning process is performed by an expensive selective printing method using either UV resist or phase change ink, however, the combination of a simple coating and laser-selective ablation processes is proposed in this study as an alternative means. As a masking material, the solar cell wafer was coated with either inexpensive wax having a low melting temperature or a fluorocarbon solution, and then, an electrode image was patterned by selectively removing the masking material using the laser. It was found that the fluorocarbon coating was not only superior to the wax coating in terms of pattern uniformity but it also increased the efficiency of the solar cell by 0.16%, as confirmed by statistical f and t tests.

• Korean Journal of Materials Research
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• v.11 no.6
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• pp.527-532
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• 2001

Dry etching of copper film using $O_2$ plasma and H(hfac) has been investigated. A one-step process consisting of copper film oxidation with an $O_2$ plasma and the removal of surface copper oxide by the reaction with H(hfac) to form volatile Cu(hfac)$_2$ and $H_2O$ was carried but. The etching rate of Cu in the range from 50 to 700 /min was obtained depending on the substrate temperature, the H(hfac)/O$_2$ flow rate ratio, and the plasma power. The copper film etch rate increased with increasing RF power at the temperatures higher than 215$^{\circ}C$. The optimum H(hfac)/O$_2$ flow rate ratio was 1:1, suggesting that the oxidation process and the reaction with H(hfac) should be in balance. Cu patterning using a Ti mask was performed at a flow rate ratio of 1:1 on 25$0^{\circ}C$\ulcorner and an isotropic etching profile with a taper slope of 30$^{\circ}$was obtained. Cu dry patterning with a tapered angle which is necessary for the advanced high resolution large area thin film transistor liquid-crystal displays was thus successfully obtained from one step process by manipulating the substrate temperature, RF power, and flow rate ratio.

• Macromolecular Research
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• v.13 no.5
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• pp.435-440
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• 2005

This study describes a method where the match of two different length scales, i.e., the patterns from self-assembled block copolymer (<50 nm) and electron beam writing (>50 nm), allow the nanometer scale pattern mask. The method is based on using block copolymers containing a poly(methyl methacrylate) (PMMA) block, which is subject to be decomposed under an electron beam, as a pattern resist for electron beam lithography. Electron beam on self assembled block copolymer thin film selectively etches PMMA microdomains, giving rise to a polymeric nano-pattern mask on which subsequent evaporation of chromium produces the arrays of Cr nanoparticles followed by lifting off the mask. Furthermore, electron beam lithography was performed on the micropatterned block copolymer film fabricated by micro-imprinting, leading to a hierarchical self assembled pattern where a broad range of length scales was effectively assembled, ranging from several tens of nanometers, through submicrons, to a few microns.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.116-121
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• 2006

Most high-k materials are well known not to be etched easily, Some problems such as low etch rate poor sidewall angle, plasma damage, and process complexity were emerged from the high-density DRAM fabrication. Chemical mechanical polishing (CMP) by a damascene process was proposed to pattern this high-k material was polished with some commercial silica slurry as a function of pH variation. Sufficient removal rate with adequate selectivity to realize the pattern mask of tera-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible. The planarization was also achieved for the subsequent multi-level processes. Our new CMP approach will provide a guideline for effective patterning of high-k material by CMP technique.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.11
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• pp.108-115
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• 2007

We have designed a high transmission C-shaped aperture using finite differential time domain (FDTD) technique. The C-shaped aperture was fabricated in the aluminum thin film on a glass substrate using a focused ion beam (FIB) milling. Nano-size patterning was demonstrated with a vacuum contact device to keep tight contact between the Al mask and the photoresist. Using 405 nm laser, we recorded a 50 nm-size dot pattern on the photoresist with the aperture and analyzed the spot size dependent on the dose illuminated on the aperture.