• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.275-278
• /
• 2003

This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2002.05a
• /
• pp.241-244
• /
• 2002

본 논문은 다치(MVL : Multiple Valued Logic) 신경망의 BP 알고리즘을 이용하여 패턴 인식에 응용하는 방법을 제안한다. 패턴처리에 필요한 원 패턴에 대한 물체 농도의 특징을 추출하고, 물체 농도의 특징을 다치로 사상시킨다. 또한 다치 신경망을 이용하여 원 패턴을 학습을 시킨 다음, 노이즈 패턴을 제거하여 원 패턴에 근접한 패턴을 인식하게 되므로, 패턴에 필요한 시간 및 기억 공간을 최소화할 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.499-503
• /
• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.6
• /
• pp.659-664
• /
• 2006

The Context-Aware system is the core technology in the Ubiquitous Computing Environment. Recently, the practical use of a sensor is magnified and the application fields of it are gradually extended in order to collect necessary context information. Context-Aware service integrates the context information which is collected by sensors, and then provides, a suitable service to a user through the process of analysis and reasoning. This service is studied in a variety of fields such as marketing, medical treatment, education and so on. In this paper, we analyze the method of recognizing surrounding context and the result of the awareness by using differential and structural property of multiple valued logic function; propose the model that provides appropriate service depending on the change of surrounding contort; confirm the applicability of the Context-aware system by showing the example of application.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.3 s.333
• /
• pp.43-50
• /
• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• Transactions on Electrical and Electronic Materials
• /
• v.17 no.6
• /
• pp.317-328
• /
• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.52-62
• /
• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.42-49
• /
• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.3
• /
• pp.102-109
• /
• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.