• 한국전자통신학회논문지
• /
• 제15권3호
• /
• pp.487-494
• /
• 2020

본 논문에서는 정적소비전력을 줄이며, 전류 모드 신호처리의 장점을 최대로 올릴 수 있는 전류 메모리 회로 설계를 제안한다. 제안하는 전류 메모리 회로는 기존의 전류 메모리 회로가 갖는 Clock-Feedthrough와 Charge-Injection 등으로 인해 데이터 저장 시간이 길어지면서 전류 전달 오차가 심해지는 문제를 최소화하며, 저전력 동작이 가능한 Current Transfer 구조에 밀러 효과(Miller effect)를 극대화하는 Support MOS Capacitor를 삽입하는 설계로, 저장 시간에 따르는 개선된 전류 전달 오차를 보였다. 매그나칩/SK하이닉스 0.35㎛ 공정으로 칩 제작을 통한 실험 결과, 저장 시간에 따르는 전류 전달 오차가 5% 이하로 개선되는 것을 검증하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1992년도 추계학술대회 논문집
• /
• pp.123-127
• /
• 1992

MOS 커패시터가 이온화 방사선에 노출되었을 경우, MOS 커패시터의 방사선 조사 효과는 소자의 전기적 특성 및 동작 수명에 심각한 영향을 일으킬 수 있다. MOS 커패시터는 (100) 방향의 P-type Si wafer 위에 산화막층을 $O^2$+T.C.E. 분위기에서 성장하였으며, 그 두께는 40~80 nm로 만들었다. MOS 커패시터에 대한 방사선 조사는 $Co^{60}-{\gamma}$선을 사용하였고, 조사선량은 $10^4{\sim}10^8$으로 조사하였다. MOS 커패시터에서 전기적 전도 특성의 방사선 조사효과는 산화막 두께와 조사선량을 변화하면서 측정된 P-type MOS 커패시터는 조사선량에 의해서 강하게 영향을 받는다는 것과 저전계 영역에서의 Ohmic 전류가 전체 선량에 의존한다는 것을 알았다. 이 결과는 방사선 조사에 의해 산화막 트랩전하와 산화막-반도체($SiO_2$-Si)계면 트랩전하에 의해서 설명 할 수 있다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
• /
• pp.130-131
• /
• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.8-9
• /
• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
• /
• pp.788-791
• /
• 1988

The C-T characteristics of nitridized MOS capacitor have been studied. The generation lifetimes were calculated using C-T transient response ans found to vary as sample condition. This is due to the non-uniformity of fast surface state. Also, This experimental curves were different from theoretical curves. The result suggests that the change in material structure (from SiO2 to Si-N-O) is important in improving minority carrier lifetime.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.195-196
• /
• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• 대한전자공학회논문지SD
• /
• 제48권5호
• /
• pp.18-24
• /
• 2011

DEM(Dynamic Element Matching) 기법중의 하나인 DWA(Data Weighted Averaging)는 멀티비트 Sigma-Delta Modulator에서 피드백 DAC의 단위요소 커패시터 부정합으로 인한 비선형성을 제거하기 위하여 널리 이용된다. 본 논문에서는 기존 DWA 구조에서 적용된 클록 타이밍을 조정하여 양자화기 데이터 코드 출력을 Latch 하는 $2^n$ Register 블록을 $2^n$ S-R latch 블록으로 대체하여 MOS Tr.를 줄임과 더불어 여분의 클록을 제거하였고, n-bit 데이터 코드를 지연시키기 위해 사용되는 2개의 n-비트 Register 블록을 1개의 n-비트 Register 블록으로 감소시켰다. 개선된 DWA 구조를 이용하여 3차 3-비트 SC(Switched Capacitor) Sigma-Delta Modulator를 설계한 후, 입력 주파수 20kHz, 샘플링 주파수 2.56MHz에서 0.1% DAC 단위 요소 커패시터 부정합을 갖도록 하여 시뮬레이션 한 결과 기존의 구조와 동일한 해상도를 얻을 수 있었고, 222개의 MOS Tr. 수를 줄일 수 있었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권4호
• /
• pp.159-163
• /
• 2003

ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 하계종합학술대회 논문집
• /
• pp.377-379
• /
• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• 전기학회논문지P
• /
• 제59권4호
• /
• pp.401-404
• /
• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.