• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.4
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1240_1241
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• 2009

In this paper, sol-gel-spin coated $Pb(ZrTi)O_3$ thin film with $ZrO_2$ buffer-layer and $PbTiO_3$ seed-layer was investigated for vibration MEMS energy harvester to scavenge power from ambient vibration via d33 piezoelectric mode. Piezoelectric thin film deposition techniques on insulating layer is the important key for $d_{33}$ mode of piezoelectric vibration energy harvester. $ZrO_2$ buff-layer was utilized as an insulating layer. $PbTIO_3$ seed-layer was applied as an inter-layer between PZT and $ZrO_2$ layer to improve the crystalline of PZT thin film. The fabricated PZT thin film had a remanent polarization of 5.3uC/$cm^2$ and the coercive field of 60kV/cm. The fabricated energy harvester using PZT thin film with PTO seed-layer generated 1.1uW of electrical power to $2.2M{\Omega}$ of load with $4.4V_{pvp}$ from vibration of 0.39g at 528Hz.

• Journal of Computing Science and Engineering
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• v.8 no.3
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• pp.129-136
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• 2014

This paper presents the equivalent circuit modelling and eigenfrequency analysis of a wideband robust capacitive radio frequency (RF) microelectromechanical system (MEMS) switch that was designed using Poly-Si and Au layer membrane for highly reliable switching operation. The circuit characterization includes the extraction of resistance, inductance, on and off state capacitance, and Q-factor. The first six eigenfrequencies are analyzed using a finite element modeler, and the equivalent modes are demonstrated. The switch is optimized for millimeter wave frequencies, which indicate excellent RF performance with isolation of more than 55 dB and a low insertion loss of 0.1 dB in the V-band. The designed switch actuates at 13.2 V. The R, L, C and Q-factor are simulated using Y-matrix data over a frequency sweep of 20-100 GHz. The proposed switch has various applications in satellite communication networks and can also be used for devices that will incorporate the upcoming IEEE Wi-Fi 802.11ad protocol.

• Transactions on Electrical and Electronic Materials
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• v.6 no.4
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• pp.135-139
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• 2005

In this paper, negative SU-8 photoresist processed at low temperature is characterized in terms of delamination. Based on a $3^3$ factorial designed experiment, 27 samples are fabricated, and the degree of delamination is measured for each. In addition, nine samples are fabricated for the purpose of verification. Employing the. neural network modeling technique, a process model is established, and response surfaces are generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. From the response surfaces generated, two significant parameters associated with delamination are identified, and their effects on delamination are analyzed. Higher PEB temperature at a fixed PEB time results in a greater degree of delamination. In addition, a higher dose of exposure energy lowers the temperature at which the delamination begins and also results in a larger degree of delamination. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.67-70
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• 2006

This paper deals with a single crystalline silicon (SCS) RF MEMS switch for telecommunication system applications. The proposed SCS switch was fabricated using a silicon-on-glass (SiOG) process and its performances in terms of RF responses, switching time, lifetime were characterized. The proposed SCS switch consists of movable plates, mechanical spring structures, which are composed of robust SCS, resulting in mechanically good stability, The measured actuation voltage was 30 V, and with this applied voltage, the insertion loss and isolation characteristics were measured to be 0.05 and 44.6 dB at 2 GHz respectively. The measured switch ON and OFF time were 13 and $9{\mu}s$, respectively. The lifetime of the fabricated switch was tested. Even after over 1 billion cycles repeated ON/OFF actuations, the switch maintained its own characteristics.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.4
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• pp.149-154
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• 2004

This paper presents a silicon probe tip for vertical probe card application. The silicon probe tip was fabricated using MEMS technology such as porous silicon micromachining and deep- RIE (reactive ion etching). The thickness of the silicon epitaxial layers was 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$, respectively. The width and length were 40 ${\mu}{\textrm}{m}$ and 600 ${\mu}{\textrm}{m}$, respectively. The probe structure was a multilayered structure and was composed of Au/Ni-Cr/Si$_3$N$_4$/n-epi layers. The height of the curled probe tip was measured as a function of the annealing temperature and time. Resistance characteristics of the probe tip were measured using a touchdown test.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.317-322
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• 2010

This paper reports the fabrication and characterization of surface micromachined poly 3C-SiC capacitive pressure sensors on silicon wafer operable in touch mode and normal mode for high temperature applications. FEM(finite elements method) simulation has been performed to verify the analytical mode. The sensing capacitor of the capacitive pressure sensor is composed of the upper metal and the poly 3C-SiC layer. Measurements have been performed in a temperature range from $25^{\circ}C$ to $500^{\circ}C$. Fabrication process of designed poly 3C-SiC touch mode capacitive pressure sensor was optimized and would be applicable to capacitive pressure sensors that are required high precision and sensitivity at high pressure and temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.343-344
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• 2008

A surface micromachined uncooled microbolometer based on the amorphous silicon was designed, fabricated, and characterized. We designed the microbolometer with a pixel size of $44\times44{\mu}m^2$ and a fill factor of about 50 % ~ 70% by considering such important factors as the thermal conductance, thermal time constant, the temperature coefficient of resistance, and device resistance. Also, we successfully fabricated the microbolometer by using surface MEMS technology. Finally, we investigated responsivity and detectivity properties depends on the active area size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.43-44
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• 2005

SU-8 is a epoxy based photoresist designed for MEMS applications, where a thick, chemically and thermally stable image is desired. But SU-8 has proven to be very sensitive to variation in processing variables and hence difficult to use in the fabrication of useful structures. In this paper, negative SU-8 photoresist processed has been characterized in terms of delamination. Based on a full factorial designed experiment. Employing the design of experiment (DOE), a process parameter is established, and analyzing of full factional design is generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.14-14
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• 2004

전자 공학 분야의 발전으로 인해 작은 구조물을 제작할 수 있는 리소그라피 (lithography) 기술이 급속하게 발전하고 있으며, 보다 작은 구조물에 대한 수요도 빠르게 증가하고 있다. 지난 수십 년간 반도체 분야에 적용 되어온 Moore's law에 의하면, 수년 내에 수십 나노 미터 크기의 특성 길이 (Critical Dimension)를 지닌 구조물을 이용하여 소자가 제작될 것 이 예견되고 있다. 반도체 공정을 응용하여 작은 구조물을 제작하는 기술은, 전자 공학 분야뿐만 아니라 광전자공학(optoelectronics) 분야, 양자 계산(quantum computing) 분야, 양자 계산(quantum computing) 분야, MEMS/NEMS, 바이오 센서(biosensor)분야 등에 다양한 응용성을 가질 것으로 예상된다.(중략)