• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.622-625
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• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.550-552
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• 2009

The negative bias temperature instability on LTPS TFTs in a darkened and an illuminated environment was investigated. Experimental results reveal that the generation of interface state density showed no change between the different NBTI stresses. The degradation of the grain boundary trap under illumination was more significant than for the darkened environment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• Information Display
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• v.6 no.5
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• pp.4-9
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• 2005

There has been a new trend to integrate various kinds of circuits by low temperature polycrystalline silicon thin film transistor (LTPS TFT) on insulator substrates to achieve System on Panel (SOP) for flat panel displays. In this paper, we will review the trend of the SOP and discuss the utility and future possibility of the SOP.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.841-844
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• 2005

There has been a new trend to integrate various kinds of circuits by low temperature polycrystalline silicon thin film transistor (LTPS TFT) on insulator substrates to achieve System on Panel (SOP) for flat panel displays. In this paper, we will review the trend of the SOP and discuss the utility and future possibility of the SOP.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1071-1074
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• 2007

6Mask CMOS process in low temperature polycrystalline silicon thin film transistors (poly-Si TFTs) has been developed and verified by manufacturing a 6Mask CMOS AMLCD panel. The novel 6Mask CMOS process is realized by eliminating the storage mask, gate mask and via open mask of conventional structure.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1123-1126
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• 2005

For creation of low temperature polycrystallinesilicon (LTPS) the line beam excimer laser annealing (ELA) is a well known and established technique in mass production. With introduction of Sequential Lateral Solidification (SLS) some aspects such as crystalline quality, throughput and flexibility regarding the substrate size could be improved, but for OLED manufacturing still further process development is necessary. This paper discusses line beam ELA and SLS techniques that might enable process engineers to make polycrystalline-silicon (poly-Si) films with a high degree of uniformity and quality as required for system on glass (SOG) and active matrix organic light emitting displays (AMOLED). Equipment requirements are discussed and compared to previous standards. SEM images of process examples are shown in order to demonstrate the viability.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.429-429
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• 2010

TFT 제조 방법 중 LTPS (Low Temperature Polycrystalline Silicon)는 저온과 저비용 등의 이점으로 인하여 flat panel display 제작에 널리 사용된다. 이동도와 전류 점멸비 등에서 이점을 가지는 ELA(Excimer Laser Annealing)가 널리 사용되고 있지만, 이 방법은 uniformity 등의 문제점을 가지고 있다. 이를 극복하기 위한 방법으로 MICC(Metal Induced Capping Crystallization)이 사용되고 있다. 이 방법은 $SiN_x$, $SiO_2$, SiON등의 capping layer를 diffusion barrier로 위치시키고, Ni 등의 금속을 capping layer에 도핑 한 뒤, 다시 한번 열처리를 통하여 a-Si에 Ni을 확산시키킨다. a-Si 층에 도달한 Ni들이 seed로 작용하여 Grain size가 매우 큰 film을 제작할 수 있다. 채널의 grain size가 클 경우 grain boundary에 의한 캐리어 scattering을 줄일 수 있기 때문에 MIC 방법을 사용하였음에도 ELA에 버금가는 소자의 성능과 안정성을 얻을 수있었다. 본 연구에서는 large grain TFT의 Gate bias stress에 따른 소자의 안정성 측정 및 분석에 목표를 두었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1075-1078
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• 2007

Negative Bias Temperature Instability (NBTI) in Eximer Laser Annealing (ELA) based Low Temperature polysilicon (LTPS) Thin-Film Transistors (TFT) was investigated. Even though NBTI is generally appeared in devices with thin gate oxide, the TFT with gate oxide thickness of 120 nm, relatively thick, also showed NBTI effect and dynamic NBTI effect is dependent on operational frequency.