• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2268-2275
• /
• 2018

This paper presents a high-efficiency low-power permanent magnet (PM) generator for the power supply of the generator exciter. In the conventional generator system, the power for the exciter is fed by the generator output power or an emergency battery for the starting. The proposed low-power PM generator can generate the proper power and voltage to excite the exciter field winding. According to the starting of the generator, the designed PM generator can supply the constant voltage to the Automatic Voltage Regulator (AVR), then it can be used to control of exciter field current for the generator. Because of the designed PM generator which is placed inside the conventional generator system, the emergency battery and Potential Transducer(PT) for AVR can be removed. Thus, the total efficiency can be improved. The proposed generator system is tested in the practical system. And the efficiency characteristic is analyzed.

• Nuclear Engineering and Technology
• /
• v.48 no.3
• /
• pp.673-683
• /
• 2016

This paper analyzes the accuracy of the methods used in calibrating the thermal power of Nigeria Research Reactor-1 (NIRR-1), a low-power miniature neutron source reactor located at the Centre for Energy Research and Training, Ahmadu Bello University, Zaria, Nigeria. The calibration was performed at three different power levels: low power (3.6 kW), half power (15 kW), and full power (30 kW). Two methods were used in the calibration, namely, slope and heat balance methods. The thermal power obtained by the heat balance method at low power, half power, and full power was $3.7{\pm}0.2kW$, $15.2{\pm}1.2kW$, and $30.7{\pm}2.5kW$, respectively. The thermal power obtained by the slope method at half power and full power was $15.8{\pm}0.7kW$ and $30.2{\pm}1.5kW$, respectively. It was observed that the slope method is more accurate with deviations of 4% and 5% for calibrations at half and full power, respectively, although the linear fit (slope method) on average temperature-rising rates during the thermal power calibration procedure at low power (3.6 kW) is not fitting. As such, the slope method of power calibration is not suitable at lower power for NIRR-1.

• ETRI Journal
• /
• v.32 no.3
• /
• pp.457-459
• /
• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• ETRI Journal
• /
• v.35 no.2
• /
• pp.226-233
• /
• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• Journal of Sensor Science and Technology
• /
• v.6 no.2
• /
• pp.137-144
• /
• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.1
• /
• pp.150-156
• /
• 2016

This paper compares the performances of permanent-magnet synchronous (PMS) and permanent-magnet vernier (PMV) machines for low-speed and high-torque applications. For comparison with the PMS machines, we consider two types of the PMV machine. The first one has surface-mounted permanent magnets (PMs) on the rotor and the other has PMs inserted on both sides of the stator and rotor. The PMS and PMV machines are designed to meet the condition of equal output power per unit volume. We analyze the magnetic fields of the machines using a two-dimensional finite element analysis (FEA). We then compare their performances in terms of the generated torque characteristics, power factor, loss, and efficiency.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.707-710
• /
• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.201-204
• /
• 2000

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.263-266
• /
• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.3058-3060
• /
• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.