• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권8호
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• 전기전자학회논문지
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• 제12권4호
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• pp.239-245
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• 2008

In this paper, a dc-dc power converter scheme with the FPGA based technology is proposed to apply for solar power system which has many features such as the good waveform, high efficiency, low switching losses, and low acoustic noises. The circuit configuration is designed by the conventional control type converter circuit using the isolated dc power supply. This new scheme can be more widely used for industrial power conversion system and many other purposes. Also, I proposed an efficient photovoltaic power interface circuit incorporated with a FPGA based DC-DC converter and a sine-pwm control method full-bridge inverter. The FPGA based DC-DC converter operates at high switching frequency to make the output current a sine wave, whereas the full-bridge inverter operates at low switching frequency which is determined by the ac frequency. As a result, we can get a 1.72% low THD in present state using linear control method. Moreover, we can use stepping control method, we can obtain the switching losses by Sp measured as 0.53W. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.

• 한국전기전자재료학회논문지
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• 제30권2호
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• pp.63-66
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• 2017

This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1518-1526
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• 2015

For now, there are some low frequency oscillations in the power system which feature low frequency oscillation with positive damping and cannot be explained by traditional low frequency oscillation mechanisms. Concerning this issue, the dynamic damping effect is put forward on the basis of the power-angle curve and the study of damping torque in this article. That is, in the process of oscillation, damping will dynamically change and will be less than that of the stable operating point especially when the angle of the stable operating point and the oscillation amplitude are large. In a situation with weak damping, the damping may turn negative when the oscillation amplitude increases to a certain extent, which may result in an amplitude-increasing oscillation. Finally, the simulation of the two-machine two-area system verifies the arguments in this paper which may provide new ideas for the analysis and control of some unclear low frequency phenomena.

• 한국통신학회논문지
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• 제31권6C호
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• pp.603-613
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• 2006

저전력 설계는 시스템의 소모전력을 줄임으로써 에너지 절약과 함께 휴대용 장치의 배터리 수명을 극대화시킴에 있어 직면한 가장 중요한 문제이다. 본 논문에서는 개량형 CSHM을 이용하여 저전력 DCT 구조를 제안하였다. 제안된 구조는 Computation Sharing Multiplication 연산 과정 중 불필요한 비트에 대한 연산을 수행하지 않는다. 실험 결과, 기존의 DCT 알고리즘과 동일한 연산 결과를 보이면서도 최대 약 9%의 소모전력이 감소하였다. 따라서 제안된 저전력 DCT 구조는 저전력 및 고성능으로 DCT 알고리즘을 처리해야하는 휴대용 멀티미디어 시스템에 적용이 가능하다.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.133-141
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• 2018

There are increasing interests on smart home systems. However, most of the existing works focus on the functionality itself. In this paper, we propose an extensible smart home system based on low power networking such as CoAP, 6LoWPAN, and Zigbee. The proposed home IoT system consists of Home APP, Home Server, Home Broker, and Power Devices. Each component of the system is connected by the low-power network technologies aforementioned. As the end device, Power Device senses the current consumption of the attached appliance and controls the power to it. Power Device reports the sensing data to Home Server via Home Broker. The Home Broker enhances the scalability of the system. Home Broker extends the service area and the user's services, and it manages the connection of the underlying devices and processes, and transmits data to Home Server from Power Devices. Through the experimental evaluation, we show that the proposed system achieves the design goals such as extensibility and low power networking.

• 한국농공학회지
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• 제37권E호
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• pp.1-9
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• 1995

It is shown that two step power transformation is more efficient for the normalization of frequency distribution with the coefficient of skewness of zero in comparison with others including SMEMAX and power transformations. It is confirmed that the design low flows calculated using power and two step power transformations used in this study are generally nearer to the observed data as compared with those of SMEMAX transformation at all return periods in the applied watersheds of the Kum, Naktong and Yongsan rivers in Korea.

• 한국정보통신학회논문지
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• 제12권3호
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• pp.555-562
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• 2008

본 논문에서는 RTL 수준에서의 클록 게이팅을 이용한 실제적인 저전력 설계 기술에 대해서 제안하고자 한다. 상위 수준의 회로 설계자에 의해 시스템의 동작을 분석하여 클록 게이팅을 위한 제어기를 이용하는 것이 가장 효율적인 전력 감소를 가져 온다. 또한 직접적으로 클록 게이팅을 수행하는 것보다는 합성툴이 자연스럽게 게이팅된 클록을 맵핑할 수 있도록 RTL 수준에서 유도하는 것이 바람직하다. RTL 코딩 단계에서부터 저전력이 고려되었다면 처음 코딩단계에서부터 클록을 게이팅 시키고, 만일 고려되지 않았다면 동작을 분석한 후에 대기 동작인 부분에서 클록을 게이팅 한다. 그리고 회로의 동작을 분석한 후에 클록의 게 이팅을 제어하기 위한 제어기를 설계하고 합성 툴에 의해 저전력 회로에 해당하는 netlist를 얻는다. 결과로부터 상위수준의 클록 게이팅에 의해 레지스터의 전력이 922 mW에서 543 mW로 42% 감소한 것을 확인할 수 있다. Power Theater 자체의 synthesizer를 이용하여 netlist로 합성한 후에 전력을 측정했을 경우에는 레지스터의 전력이 322 mW에서 208 mW로 36.5% 감소한 것을 확인할 수 있다.