• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.12
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• pp.1857-1863
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• 2010

We present the fabrication and characterization of transparent carbon nanotube film (CNF) piezoresistors. CNFs were fabricated by vacuum filtration methods with 65?92% transmittance and patterned on Au-deposited silicon wafer by photolithography and dry etching. The patterned CNFs were transferred onto poly-dimethysiloxane (PDMS) using the weak adhesion property between the silicon wafer and the Au layer. The transferred CNFs were confirmed to be piezoresistors using the equation of concentrated-force-derived resistance change. The gauge factor of the CNFs was measured to range from 10 to 20 as the resistance of the CNFs increased with applied pressure. In polymer microelectromechanical systems, CNF piezoresistors are the promising materials because of their high sensitivity and low-temperature process.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1361-1363
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• 1998

Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment, $POCl_3$ gettering, and examined carrier lifetime. This paper focuses on resistivity variation effect due to grain boundary of poly-Si. The resistivity of the inner grain was $2.2{\Omega}-cm$, on the grain boundary$2.3{\Omega}-cm$, across the grain boundary $2.6{\Omega}-cm$. A measured resistivity varied depending on how many grains were included inside the four point probes. The resistivity increased as the number of grain boundaries increased. Our result can contribute to achieve high conversion efficiency of poly-Si solar cell by overcoming the grain boundary influence.

• Tribology and Lubricants
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• v.18 no.1
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• pp.1-8
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• 2002

Nano adhesion and friction between a $Si_{3}N_{4}$ AFM(atomic force microscope) tip and thin silver films were experimentally studied. Tests were performed to measure the nano adhesion and friction in both AFM and LFM(lateral force microscope) modes in various range of normal loads. Thin silver films deposited by IBAD (ion beam assisted deposition) on Si-wafer (100) and other Si-wafers of different surface roughness were used. Results showed that nano adhesion and friction decreased with the surface roughness. When the Si surfaces were coated by pure silver, the adhesion and friction decreased. But the adhesion and friction were not affected by the thickness of IBAD silver coating. As the normal force increased, the adhesion forces of bare Si-wafer and IBAD silver coating film remained constant, but the friction forces increased linearly. Test results suggested that the friction was mainly governed by the adhesion as long as the load was low.

• Journal of the Korean institute of surface engineering
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• v.40 no.3
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• pp.138-143
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• 2007

The effects of texturing and anti-reflection coating on the reflection properties of multi-crystalline silicon solar cell have been investigated. The chemical solutions of alkaline and acidic etching solutions were used for texturing at the surface of multi-crystalline Si wafer. Experiments were performed with various temperature and time conditions in order to determine the optimized etching condition. Alkaline etching solution was found inadequate to the texturing of multi-crystalline Si due to its high reflectance of about 25%. The reflectance of Si wafer texturing with acidic etching solution showed a very low reflectance about 10%, which was attributed to the formation of homogeneous. Also, deposition of ITO anti-reflection coating reduced the reflectance of multi-crystalline si etched with acidic solution($HF+HNO_3$) to 2.6%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1103-1107
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• 2005

Single-crystal silicon thin films on glass (SOG) and on fused-quartz (SOQ) were prepared using wafer bonding and hydrogen-induced layer transfer. Thinfilm transistors (TFTs) were subsequently fabricated. The high-temperature processed SOQ TFTs show better device performance than the low-temperature processed SOG TFTs. Tensile and compressive strain was measured respectively on SOQ and SOG. Consistent with the tensile strain, enhanced electron effective mobility was measured on the SOQ TFTs.

• Journal of Sensor Science and Technology
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• v.16 no.1
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• pp.62-67
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• 2007

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin (Au/Sn) eutectic solder bonding. The membrane chip has 2.5 mm${\times}$2.5 mm, $0.5{\mu}m$ thick low stress silicon nitride membrane, 2 mm${\times}$2 mm Au/Ni/Cr membrane electrode, and $3{\mu}m$ thick Au/Sn layer. The backplate chip has 2 mm${\times}$2 mm, $150{\mu}m$ thick single crystal silicon rigid backplate, 1.8 mm${\times}$1.8 mm backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50-60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is $39.8{\mu}V/Pa$ (-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.26-31
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• 2007

The goal of this study is to determine if High Pressure Micro Jet (HPMJ) conditioning can be used as a substitute for, or in conjunction with, conventional diamond pad conditioning. Five conditioning methods were studied during which 50 ILD wafers were polished successively in a 100-mm scaled polisher and removal rate (RR), coefficient of friction (COF), pad flattening ratio (PFR) and scanning electron microscopy (SEM) measurements were obtained. Results indicated that PFR increased rapidly, and COF and removal rate decreased significantly, when conditioning was not employed. With diamond conditioning, both removal rate and COF were stable from wafer to wafer, and low PFR values were observed. SEM images indicated that clean grooves could be achieved by HPMJ pad conditioning, suggesting that HPMJ may have the potential to reduce micro scratches and defects caused by slurry abrasive particle residues inside grooves. Regardless of different pad conditioning methods, a linear correlation was observed between temperature, COF and removal rate, while an inverse relationship was seen between COF and PFR.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Korea-Australia Rheology Journal
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• v.14 no.2
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• pp.63-70
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• 2002

Chemical mechanical planarization (CMP) is the polishing process enabled by both chemical and mechanical actions. CMP is used in the fabrication process of the integrated circuits to achieve adequate planarity necessary for stringent photolithography depth of focus requirements. And recently copper is preferred in the metallization process because of its low resistivity. We have studied the effects of chemical reaction on the polishing rate and surface planarity in copper CMP by means of numerical simulation solving Navier-Stokes equation and copper diffusion equation. We have performed pore-scale simulation and integrated the results over all the pores underneath the wafer surface to calculate the macroscopic material removal rate. The mechanical abrasion effect was not included in our study and we concentrated our focus on the transport phenomena occurring in a single pore. We have observed the effects of several parameters such as concentration of chemical additives, relative velocity of the wafer, slurry film thickness or ash)tract ratio of the pore on the copper removal rate and the surface planarity. We observed that when the chemical reaction was rate-limiting step, the results of simulation matched well with the experimental data.