• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• International journal of advanced smart convergence
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• v.7 no.3
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• pp.23-36
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• 2018

In wireless communication, efficient spectrum usage is an issue that has been an attractive research area for many technologies. Recently new technologies innovations allow compact radios to transmit with power efficient communication over very long distances. For example, Low-Power Wide Area Networks (LPWANs) are an attractive emerging platform to connect the Internet-of-Things (IoT). Especially, LoRa is one of LPWAN technologies and considered as an infrastructure solution for IoT. End-devices use LoRa protocol across a single wireless hop to communicate to gateway(s) connected to the internet which acts as a bridge and relays message between these LoRa end-devices to a central network server. The use of the (ISM) spectrum sharing for such long-range networking motivates us to implement spectrum sensing testbed for cognitive radio network based on LoRa and GNU radio. In cognitive radio (CR), secondary users (SUs) are able to sense and use this information to opportunistically access the licensed spectrum band in absence of the primary users (PUs). In general, PUs have not been very receptive of the idea of opportunistic spectrum sharing. That is, CR will harmfully interfere with operations of PUs. Subsequently, there is a need for experimenting with different techniques in a real system. In this paper, we implemented spectrum sensing for cognitive radio networks based on LoRa and GNU Radio, and further analyzed corresponding performances of the implemented systems. The implementation is done using Microchip LoRa evolution kits, USRPs, and GNU radio.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.593-602
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• 2020

Recently, as research on smart farms has been actively conducted, systems for efficiently cultivating crops have been introduced and various energy systems using renewable energy such as solar, geothermal and wind power generation have been proposed to save the energy. In this paper, we propose a new and renewable energy convergence system for crops that provides energy independence and improved crop cultivation environment. First, we present LPWA-based communication node and gateway for ICT-based data collection. Then we propose an integrated monitoring server that collects energy data, crop growth data, and environmental data through a communication node and builds it as big data to perform optimal energy management that reflects the characteristics of the environment for cultivating crops. The proposed system is expected to contribute to the production of low-cost, high-quality crops through the fusion of renewable energy and smart farms.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.4
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• pp.695-702
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• 2020

Recently, as research on smart farms has been actively conducted, indoor environment control, such as a green house, has reached a high level. However, In the field of forestry where cultivation is carried out in outdoor, the use of ICT is still insufficient. In this paper, we propose LPWA-based forest growth environment collection and big data analysis system using ICT technology. The proposed system collects and transmits the field cultivation environment data to the server using small solar power generation and LPWA technology based on the oneM2M architecture. The transmitted data is constructed as big data on the server and utilizes it to predict the production and quality of forest products. The proposed system is expected to contribute to the production of low-cost, high-quality crops through the fusion of renewable energy and smart farms. In addition, it can be applied to other industrial fields that utilize the oneM2M architecture and monitoring the growth environment of agricultural crops in the field.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1654-1661
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• 2020

Internet of Things(IoT) technology can remotely collect and control a sensing information of device by attaching a small communication device to equipment that does not support communication. Low-Power Wide-Area Network (LPWAN), a low-power, long-distance communication technology, was proposed to support IoT technology, and Long Range(LoRa) is representative. Various systems, including network device, can collect and control the status information of device in real time through remote access. However, when a network failure occurs, remote access and status monitoring are impossible unless there is a separate additional network. To overcome this problem, in this paper, we propose an independent remote device management system that can be easily attached to device, which monitors and controls equipment remotely using an independent network. We will design and implement the proposed system, via which we will show its practicality and expandability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.