• Journal of Korea Society of Industrial Information Systems
• /
• v.17 no.4
• /
• pp.17-23
• /
• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• Journal of electromagnetic engineering and science
• /
• v.17 no.4
• /
• pp.191-196
• /
• 2017

Microwave wireless power transmission (MWPT) is a promising technique for low and medium power applications such as wireless charging for sensor network or for biomedical chips in case with long ranges or in dispersive media such. A key factor of the MWPT technique is its efficiency, which includes the wireless power transmission efficiency and the radio frequency (RF) to direct current (DC) voltage efficiency of RF-DC converter (which transforms RF energy to DC supply voltage). The main problem in designing an RF-DC converter is the nonlinear characteristic of Schottky diodes; this characteristic causes low efficiency, higher harmonics frequency and a change in the input impedance value when the RF input power changes. In this paper, rather than using harmonic termination techniques of class E or class F power amplifiers, which are usually used to improve the efficiency of RF-DC converters, we propose a new method called "optimal input impedance" to enhance the performance of our design. The results of simulations and measurements are presented in this paper along with a discussion of our design concerning its practical applications.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.1605-1607
• /
• 2000

In this paper, the design of class AB BiCMOS log-domain filter for low-voltage and low-power was proposed. This filter is consist of a log-domain integrator using folded junctions with capacitor connected to emitter and it's class AB structure. A comparison between the proposed class AB BiCMOS log-domain filter and classical class A BiCMOS log-domain filter is drawn on the basis of SNR, THD and the frequency response. This comparison shows proposed filter are more than good SNR, THD and frequency characteristics than more class A log-domain filter for low voltage and low power.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.5 no.3
• /
• pp.69-75
• /
• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.169-172
• /
• 2002

A protection integrated circuit which enables the stable operation of the rechargeable battery should be designed with a low-power architecture because it consumes the power of the battery. This paper proposed a low-power scheme especially when the several series-connected batteries are provided. By adopting a time sharing control of the batteries, the chip size and power consumption could be reduced.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.851-854
• /
• 2003

The low power motion estimation for MPEG-4 is a soft-core for hardwired motion estimation block in MPEG-4. This motion estimation is modified by 10 difference mode. So, this motion estimation decrease a power consumption compare conventional step search. This modified 4SS Low power Motion Estimation has been tested and verified to be valid for implementation of FPGA. The average PSNR between the original image and the motion-compensated image is 28.25dB. And Power consumption is 26mW.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.1
• /
• pp.10-16
• /
• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

• The Journal of Information Technology
• /
• v.3 no.1
• /
• pp.117-124
• /
• 2000

This paper proposes a new heuristic algorithm of a low power hardware allocation for Design Automation. The proposed algorithm works on scheduled input graph and allocates functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. The low power factor of the capacitance is reduced during the allocation. As the resource number reduce maximal . This paper shows the effectiveness of the algorithm by comparing experiments of existing system of the non low power.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.62-68
• /
• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• The Journal of the Korea Contents Association
• /
• v.10 no.12
• /
• pp.10-17
• /
• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.