• 한국산업정보학회논문지
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• 제21권1호
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• pp.17-25
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• 2016

본 논문은 동기회로에서 누설 전류를 줄이기 위해서 사용되는 파워 스위치 구조를 결합한 새로운 구조의 저전력 비동기 회로 설계 방법을 제안하고자 한다. Static 방식, Semi-static 방식과 같은 기존의 지연 무관방식의 비동기 방식과 비교해서 다소 속도의 손해는 있지만, 파워 스위치에 의해서 데이터가 없는 상태에서는 누설 전력을 줄일 수 있고, 전체 사이즈가 작아짐으로써 데이터가 입력되는 순간의 스위칭 전력도 줄일 수 있는 장점이 있다. 따라서, 제안된 방법은 속도보다 저전력을 기본으로 하는 사물인터넷 시스템에서 요구되는 전전력 설계 방법이 될 것이다. 본 논문에서는 새로운 방식의 비동기 회로를 사용하여 $4{\times}4$곱셈기를 0.11um 공정으로 설계하고, 기존의 비동기 방식의 곱셈기와 스피드, 누설 전류, 스위칭 파워, 회로 크기 등을 비교하였다.

• ETRI Journal
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• 제24권6호
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• 한국통신학회논문지
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• 제21권5호
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• pp.1221-1229
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• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제5권2호
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• pp.102-107
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• 2005

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

• ETRI Journal
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• 제26권6호
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• 전자공학회논문지C
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• 제35C권7호
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• pp.46-58
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• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• 한국지능시스템학회논문지
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• 제10권5호
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• pp.478-486
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• 2000

본 논문에서는 CMOS 디지털 회로상의 플립플롭의 위치를 이동시키는 리타이밍 변환에 유전자 알고리즘을 적용하여 회로의 최적 동작 속도를 유지하면서 전력의 소모를 줄일 수 있는 설계 방법을 제안한다. 제안된 설계 방법은 최적 속도를 구현하는 리타이밍 단계와 유전자 알고리즘이 적용되는 저전력 리타이밍의 두 단계로 이루어진다. 제안된 저전력 리타이밍 설계 도구를 예제 회로의 설계에 적용하고 설계된 회로의 성능을 Synopsys시의 Design Analyzer로 평가한 결과, 임계 경로 지연은 약 30~50% 가량 감소하였으며 동적 전력 소모는 약 1.4~18.4% 가량 감소함을 관찰하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.221-225
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• 2014

Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.159-162
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• 2007

Comparative study on a low cost sustaining driver with single and dual path energy recovery circuits for plasma display panels (PDPs) is shown in this paper. The cost of PDPs has been still high and about half of the cost has been occupied by driving circuit. A simple sustaining driver is proposed to reduce the cost and size of driving circuit. The proposed driver has small number of devices and reactive components and there are two methods for charging and discharging PDPs such as single and dual path energy recovery circuits. A comparative research on two-types of energy recovery path is practiced to evaluate performance. As a result, the dual energy recovery path circuit has low power consumption, low surge current and high performance. To verify those results, experiment will be shown with 42-inch HD panel.