• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.3
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• pp.677-685
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• 2017

Supply rate is very low because conventional smart system of streetlight management requires a lot of time and cost until now. In this paper, we demonstrated maintaining system for streetlight which uses LoRaWAN to solve following those reasons. Using LoRaWAN is subject to build long range and low power communication. Furthermore, it helps to make low initial and cost for maintenance. Detecting problem of streetlight in real time and controling streetlight based on situation and environment are additional benefits. This system on control part is carried by administrator in GUI environment. Finally, we verified the proposed system of performance for LoRaWAN communication and sensor accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

• Journal of Korean Society on Water Environment
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• v.23 no.6
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• pp.850-862
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• 2007

This study was carried out to survey the actual conditions of wastewater treatment facilities to obtain basic data for the management of wastewater from industrial complexes in Chungcheongnam-do province. Wastewater production flow per site area by watersheds was $49.2m^3/km^2/d$ for Sapgyoho, $8.1m^3/km^2/d$ for Anseongcheon, $5.7m^3/km^2/d$ for Seohae, and $2.9m^3/km^2/d$ for Geumgang. Sapgyoho showed 75% of the total production flow, which was the highest value, Geumgang showed 4% of total flow, which was the lowest value. Average total extra rate as production flow/capacity flow in the wastewater treatment facilities for industrial complex is 49%. Considering by watersheds, the extra rates of Seohae, Geumgang, Anseongcheon, and Sapgyoho, are 73%, 65%, 62%, and 33% respectively. This means that the design of capacity flow in wastewater treatment facilities was too large. Effluent concentration of wastewater treatment facilities did not exceed discharge limit mostly. The removal efficiency rate for water quality item was 90% in BOD, 70% in COD, 80% in SS, 30 to 80% in TN, and 20 to 90% in TP, so the organic removal was good, but the nutrient removal was low and interval of variation was high. The removal efficiency rate of the agricultural was industrial complexes is lower than the national and local complexes. The construction cost of the wastewater treatment facilities in Chungcheongnam-do was $1,756Won\;per\;m^3$, treatment cost was $189Won\;per\;m^3$, and they were about two times and 1.2 times higher than the nation-wide cost, respectively. The treatment cost consists of 39% for man power, 21% for chemical, 16% for power, 11% for sludge treatment, and 13% for others.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.846-851
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• 2007

The wireless sensor network is one of the most practical and cost-effective solutions for monitoring systems covering wild and wide area such as wildfire monitoring. However, the RF distance between sensor nodes is very short due to the need of low power consumption of the sensor node, so the number of sensor nodes to be deployed in the target area is more than tens of thousands. In this paper, we design and analyze the deployment issues as well as re-deployment problem occurred when the battery is exhausted. We also propose the needs and solutions for coverage problem in dynamic deployment. By the experimental evaluations, we analyze the packet success ratio between sensor nodes under various environments such as obstacles and variable distances.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2187-2193
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• 2010

A specific radar system can be implemented more easily using the frequency modulated continuous wave comparing with the pulse Doppler radar. It also has the advantage of LPI (low probability of interception) because of the low power and wide bandwidth characteristics. These radars are usually used to cover the short range area and to obtain the high resolution measurements of the target range and velocity information. The transmitted waveform is used in the mixer to demodulate the received echo signal and the resulting beat signal can be obtained. This beat signal is analyzed using the FFT method for the purpose of clutter removal, detection of a target, extraction of velocity and range information, etc. However, for the case of short signal acquisition time, this FFT method can cause the serious leakage effect which disables the detection of weaker echo signals masked by strong side lobes of the clutter. Therefore, in this paper, the weighting window method is analyzed to suppress the strong side lobes while maintaining the proper main lobe width. Also, the results of FFT beat spectrum analysis are shown under various environments.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.364-370
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• 2011

The Hilbert transform performs a role to transform band pass signals into low pass signals in wireless communication systems. The operation of Hilbert transform is based on a convolution process which is required adding and multiplying calculations. When the Hilbert transform is designed and hardware-implemented at gate level, the adding and multiplying operation requires a high power consumption and a occupation of wide area on a chip. So the results of adding and multiplying operation cause to degrade the performance of implemented system. In this paper, the new Hilbert transformer is proposed, which has a low hardware complexity by application of MAG(Minimum Adder Graph) algorithm. The proposed Hilbert transformer was simulated in ISE environment of Xilinx and showed the reduction of hardware complexity comparing with the number of gate in the conventional Hilbert transformer.