• ETRI Journal
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• v.25 no.5
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Korean Solar Energy Society
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• v.31 no.4
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• pp.19-26
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• 2011

We are carried out power performance testing for 3MW wind turbine system at Je-ju wind turbine testing Site and analyzed measured data which was stored through monitoring system. In this paper, we described the power performance testing results and analyzed an uncertainty of measured data sets. The power curve with measured power data is closely coincide with designed power curve except for the low wind speed sections(4m/s~7m/s) and the annual energy production which is given Ray leigh distribution was included with 1.5~5.9% of uncertainty in the wind speed region as 4~11m/s. Although the deviation of curve between measured power and designed power is high, the difference of annual energy production is low in the low wind speed region.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.961-963
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• 2000

Most of the application standard of the low-voltage devices have applied one the IEC standard another the UL standard. European union applied the IEC60947-1 standard has not exceed 1000V a.c. or 1500V d.c.. Therefore. it is necessary to the low-voltage device has expended for rated operational voltage with our products. The export of European market shall be made for the CE-Marking in accordance with IEC60947-1 ( Low-voltage switchgear and controlgear). We shall be considered for the requirement with the IEC standard. In this time to study for power supply system at EU ( European union. At that time for design and development in order to the construction and test method among the study for the rated insulation voltage at less then 690V.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.253-257
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• 2003

This paper presents the Development of Switching Power Supply for testing communication equipment. The communication equipment need many kinds of voltage(-48V,27V,12V,5V,3.3V), and in case of low voltage needs large current($10{\sim}20A$). The previous Linear Power Supply was very heavy, has low efficiency and poor power-factor for testing communication equipment. This development has good efficiency and high power-factor using switch mode power supply technique. This Development of Switching Power Supply is composed of eight converters. The principles of operation, feature, and design considerations are illustrated and verified through the experiment with 600W prototype.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1393-1405
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• 2017

It is well known that duty-cycling control by dynamically adjusting the polling interval according to the traffic loads can effectively achieve power saving in wireless sensor networks. Thus, there has been a significant research effort in developing polling interval adaptation schemes. Especially, Dynamic Low Power Listening (DLPL) scheme is one of the most widely adopted open-looping polling interval adaptation techniques in wireless sensor networks. In DLPL scheme, if consecutive idle (busy) samplings reach a given fixed threshold, the polling interval is increased (decreased). However, due to the trial-and-error based approach, it may significantly deteriorate the system performance depending on given threshold parameters. In this paper, we propose a novel DLPL scheme, called SDL (Sequential hypothesis testing based Dynamic LPL), which employs sequential hypothesis testing to decide whether to change the polling interval conforming to various traffic conditions. Simulation results show that SDL achieves substantial power saving over state-of-the-art DLPL schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.