• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.190-195
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• 2000

This paper presents the fabrication of the LNA which is operating at 2.13∼2.16 GHz for IMT-2000 lot-end receiver using series feedback and resistive decoupling circuit. Series feedback added to the source lead of a transistor keep the low noise characteristics and drop the input reflection coefficient of amplifier simultaneously. Also, it increases the stability of the LNA. Resistive decoupling circuit is suitable for input stage matching because a signal at low frequency is dissipated by a resistor in the matching network The amplifier consist of GaAs FET ATF-10136 for low noise stage and VNA-25 which is internally matched MMIC for high gain stage. The amplifier is fabricated with both the RF circuits and self bias circuit on the Teflon substrate with 3.5 permittivity. The measured results of the LNA which is fabricated using above design technique are presented more than 30 dB in gain P$\_$ldB/ 17 dB and less than 0.7 dB in noise figure, 1.5 in input$.$output SWR(Standing Wave Ratio).

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.319-322
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• 1998

A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.443-447
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• 2005

In this paper, a low noise amplifier(LNA) in a receiver of a Low Noise Block Down Converter (LNB) for direct broadcasting service(DBS) is implemented using GaAs HEMT. The 2-stage LNA is designed for the bandwidth of 11.7GHz - 12.2GHz. The result of a simulation of the LNA using Advanced Design System(ADS) shows that the noise figure is less than 1.4dB, the gain is greater than 23dB and the flatness is 1dB in the bandwidth of 11.7 to 12.2GHz.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.1-5
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• 2010

This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

• Nuclear Engineering and Technology
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• v.56 no.2
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• pp.568-574
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• 2024

The development of radiation-tolerant radio-frequency (RF) systems can be a solution for applications in extreme radiation environments, such as nuclear power plant monitoring and space exploration. Among the crucial components within an RF system, the low noise amplifier (LNA) stands out due to its vulnerability to TID effects, mainly relying on transistors as its main devices. In this study, the TID effects in the LNA using standard 0.18 ㎛ complementary metal oxide semiconductors (CMOS) technology are estimated and analyzed. The results show that the LNA can withstand absorbed radiation up to 100 kGy. The S₂₁, S₁₁, noise figure (NF), stability (K), and linearity of the third input intercept point (IIP3) slightly shifted from the initial values of 0.8312 dB, 0.793 dB, 0.00381 dB, 1.34406, and 2.36066 dBm, respectively which are still comparable to the typical performances. Moreover, the standard 0.18 ㎛ technology has demonstrated its radiation tolerance, as it exhibits negligible performance degradation in the conventional LNA even when exposed to radiation levels up to 100 kGy. In this context, simulation approach offers a means to predict the TID effects and estimate the radiation exposure limit for electronic devices, particularly when transistors are used as the primary RF components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.48-51
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• 2009

One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.289-294
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• 2008

A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

• Journal of electromagnetic engineering and science
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• v.7 no.2
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• pp.91-95
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• 2007

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through $0.13{\mu}m$ RF CMOS process for WiBro system. The designed LNA achieves +7.8 dBm of input-referred 3^{rd}$-order intercept point (IIP3) with 13.2 dB of Power Gain, 1.3 dB of noise figure and 5.7mA @1.5V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 dB without degrading other features such as gain and noise figure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.353-358
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• 1998

This paper presents development of a LNA operating at 1.71 ∼ 1.18 GHz used for a receiver of KOREA PCS base station and transponder. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA and suitable for input stage matching. The LNA consists of low noise GaAs FET ATF-10136 and internally matched VNA-25. The LNA is fabricated with both the RF circuit and the self-bias circuits in aluminum housing. As a result, the characteristics of the LNA implemented here shows 30 dB in gain and 0.85 dB in noise figure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.