• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• Journal of IKEEE
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• v.17 no.4
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• pp.544-549
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• 2013

This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.27-35
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• 2016

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.17-22
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• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.240-245
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• 2019

This paper is a study result on long distance transmission of underwater acoustic sensor data over cable. The data transceiver is designed using the LVDS (Low Voltage Differential Signaling) transmission scheme, and the jitter characteristics are analyzed by measuring the long distance transmission signal through the cable. In order to reduce the jitter, a pre-emphasis technique is applied to compensate the transmitting signal to be attenuated by long distance transmission, and the transmission characteristics were verified according to the distance.

• Journal of IKEEE
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• v.13 no.4
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• pp.103-109
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• 2009

We report an efficient jitter reduction technique in an analog fier-optic link employing a Mach-Zehnder modulator followed by an erbium-doped fiber amplifier. By adjusting the modulator-bias to $0.089V_{\pi}$, we could increase the RF gain up to 10.65 dB for 10 GHz RF signal and reduce the random jitter by 46.5%, max, at an input optical power of -0.11 dBm to the EDFA.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.5 no.3 s.11
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• pp.13-23
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• 2006

The system using UWB is processing brisk study with Bluetooth among the wireless access that is major technology in Telematics. The low complexity and cost for realization is advantage of UWB have communication of high speed. Mamy papers have published on the timing jitter effect on system performance except for the UWB system. In this paper, we analyze the effect of timing jitter on M-ary UWB system using orthogonal Hermite pulse and perform the simulation to show symbol error rate performance. For theoretical analysis, we derive correlation function of orthogonal Hermits pulse with closed form, and as well upper bound of Symbol Error Probability for M-ary orthogonal Hermite pulse system mathematically. It is found that numerical analysis is accurate enough through simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.69-76
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• 2015

In this paper, we propose and analyze a M-ary transmission scheme in time hopping ultra-wide band(UWB) system using mutually orthogonal modified Hermite polynomial(MHP) pulses. The proposed M-ary transmission scheme employs the orthogonal property between different ordered pulses and N data bits make the M-ary signals by linear combination of M MHP pluses. The theoretical analysis and simulation results show that the proposed system has better performance and higher data rate than conventional M-ary UWB system. We derive the general form of correlation function for MHP pulses and analyze bit error rate(BER) performance over additive white Gaussian noise(AWGN) with the presence of timing jitter. We show that the proposed system has the improved BER performance and robustness to timing jitter and low power spectrum density compared with conventional M-ary UWB system.