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http://dx.doi.org/10.5573/ieie.2016.53.2.027

A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices  

Baek, Ye-Seul (Electrical and Electronic Engineering, Chung-Ang University)
Lee, Jeong-Yun (Electrical and Electronic Engineering, Chung-Ang University)
Ryu, Hyuk (Electrical and Electronic Engineering, Chung-Ang University)
Lee, Jongyeon (Electrical and Electronic Engineering, Chung-Ang University)
Baek, Donghyun (Electrical and Electronic Engineering, Chung-Ang University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.2, 2016 , pp. 27-35 More about this Journal
Abstract
A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.
Keywords
audio device; frequency synthesizer; phase-locked loop (PLL); low jitter;
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