• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Archives of design research
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• v.18 no.1 s.59
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• pp.17-26
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• 2005

Nowadays, display-contents are developing to an informative environment. that is under the logic of the media operating system. To perceive the media-environments and produce the cultural contents, the cultural designers seek to understand a skin structure from making up for shape. To appreciate operating system in data and database is not only systematization of form and contents of visual contents but also variety contents into multiple-platform and integrative environments. These days, the spectacle exhibition try to express for their surface design between algorithm of data and database. the information is expressing aesthetic which means presents the integrated contents through the play instinct environment to end-user. That was given web or game to participation is developing with the cellular device and ubiquitous computing system. in the linear perspective, the end-user should be immerse more and more hyper-simulation system because of the operating algorithm of database. To do this, human have need to get the information-ability from multi-platform society. In the virtual environment, database offer the experience of an unheard-of event to end-user that prepare the participants the circumstances priority of signifiers. To do that already based on a fixed sensibility endow with narrative of the freshness- experience.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of Korean Society of Steel Construction
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• v.24 no.3
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• pp.325-336
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• 2012

Smart base isolation systems developed for structures in high seismic regions cannot be directly applied to structures in regions of low-to-moderate seismicity, such as Korea. Therefore, the problems that occur by applying the smart base isolation system for high seismic regions to the structures in regions of low-to-moderate seismicity have been investigated in this study. To this end, a five-story building is used as an example, and an MR damper and low damping elastomeric bearings were used to compose a smart base isolation system. Artificial earthquakes are simulated for ground motions in regions of high and low-to-moderate seismicity. Based on numerical simulation results, the MR damper capacity that can provide good control is quite different among regions of high and low-to-moderate seismicity. Moreover, it is noted that the properties of a smart base isolation system for the regions of low-to-moderate seismicity should be carefully designed because the base isolation effects of the smart base isolation system for high seismic regions deteriorate when it is applied to the structures in regions of low-to-moderate seismicity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.85-98
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• 1998

This paper proposes a new design method of neuro-FLC by the Lamarckian co-adaptation scheme that incorporates the backpropagation learning into the GA evolution in an attempt to find optimal design parameters (fuzzy rule base and membership functions) of application-specific FLC. The design parameters are determined by evolution and learning in a way that the evolution performs the global search and makes inter-FLC parameter adjustments in order to obtain both the optimal rule base having high covering value and small number of useful fuzzy rules and the optimal membership functions having small approximation error and good control performance while the learning performs the local search and makes intra-FLC parameter adjustments by interacting each FLC with its environment. The proposed co-adaptive design method produces better approximation ability because it includes the backpropagation learning in every generation of GA evolution, shows better control performance because the used COG defuzzifier computes the crisp value accurately, and requires small workspace because the optimization procedure of fuzzy rule base and membership functions is performed concurrently by an integrated fitness function on the same fuzzy partition. Simulation results show that the Lamarckian co-adapted FLC produces the most superior one among the differently generated FLCs in all aspects such as the number of fuzzy rules, the approximation ability, and the control performance.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• Journal of the Korean Institute of Intelligent Systems
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• v.3 no.2
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• pp.18-35
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• 1993

The water level control system of the steam generator in a pressurized water reactor and its control problems are analysed. In this work the stable control strategy during the low power operation and transient states is studied. To solve the problem, a fuzzy logic control method is applied as a basic algorithm of the controller. The control algorithm is based on the operator's knowledges and the experiences of manual operation for water level control at the compact nuclear simulator set up in Korea Atomic Energy Research Institute. From a viewpoint of the system realization, the control variables and rules are established considering simpler tuning and the input-output relation. The control strategy includes the dynamic tuning method and employs a substitutional information using the bypass valve opening instead of incorrectly measured signal at the low flow rate as the fuzzy variable of the flow rate during the pressure control mode of the steam generator. It also involves the switching algorithm between the control valves to suppress the perturbation of water level. The simulation results show that both of the fine control action at the small level error and the quick response at the large level error can be obtained and that the performance of the controller is improved.