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A CMOS 16:1 Binary-Tree Multiplexer applying Delay Compensation Techniques  

Shon, Kwan-Su (Program in Micro/Nano Systems, Korea University)
Kim, Gil-Su (Dept. of Electronics and Computer Eng., Korea University)
Kim, Kyu-Young (Dept. of Electronics and Computer Eng., Korea University)
Kim, Soo-Won (Dept. of Electronics and Computer Eng., Korea University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 21-27 More about this Journal
Abstract
This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.
Keywords
Multiplexer; binary-tree; delay-compensation;
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  • Reference
1 B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, New York, 2002
2 J. Cao, M. Green, A. Momtaz, K. Vakilian, D. Chung, J. K.-C., M. Caresosa, X. Wang, T. W-Guan, C. Yijun, L. Fujimori, and A. Hairapetian, "OC-192 transmitter and receiver in standard 0.18-$\mu$m CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1768-1780, Dec. 2002   DOI   ScienceOn
3 A. Hendarman, E. A. Sovero, X. Xu, and K. Witt, "STS-768 multiplexer with full rate output data retimer in InP HBT," 24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, pp. 211-214, Oct. 2002
4 C. L. Stout and J. Doernberg, "10 Gb/s silicon bipolar 8 : 1 multiplexer and 1 : 8 demultiplexer," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 339-343, March 1993   DOI   ScienceOn
5 Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, and Beomsup Kim, "A Four-Channel 3.125-Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer," IEEE J. Solid-State Circuits, vol. 40, no. 2, Feb. 2005
6 P. Heydari, R. Mohanavelu, "Design of ultrahigh-speed low-voltage CMOS CML buffers and latches," IEEE Trans. VLSI Systems, vol. 12, no. 10, pp. 1081-1093, Oct. 2004   DOI   ScienceOn
7 T. Palkert, "A review of current standards activities for high speed physical layers," Proc. 5th International Workshop on System-on-Chip for Real-Time Applications, pp. 495-499, July 2005