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A Study on The Design of China DSRC System SoC  

Shin, Dae-Kyo (SoC Platform Research Center, Korea Electronics Technology Institute)
Choi, Jong-Chan (SoC Platform Research Center, Korea Electronics Technology Institute)
Lim, Ki-Taeg (SoC Platform Research Center, Korea Electronics Technology Institute)
Lee, Je-Hyun (School of Electrical Engineering, Dongyang Technical College)
Publication Information
전자공학회논문지 IE / v.46, no.4, 2009 , pp. 1-7 More about this Journal
Abstract
The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.
Keywords
ITS; ETC; DSRC; low power consumption; SoC;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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