• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.53-60
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• 2007

In a known plaintext scenario, fast correlation attack is very powerful attack on stream ciphers. Most of fast correlation attacks consider the cryptographic problem as the suitable decoding problem. In this paper, we introduce advanced multi-pass fast correlation attack which is based on the fast correlation attack, which uses parity check equation and Fast Walsh Transform, proposed by Chose et al. and the Multi-pass fast correlation attack proposed by Zhang et al. We guess some bits of initial states of the target LFSR with the same method as previously proposed methods, but we can get one more bits at each passes and we will recover the initial states more efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.832-835
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• 2004

In this paper, we proposed a blind watermarking algorithm to use characteristics of a scalar quantizer which is similar with the recommended in the JPEG2000 and JPEG. This algorithm shifts a quantization index according to the value of each watermark bit to prevent losing the watermark information during the compression by quantization. Therefore, the watermark is embedded during the process of quantization, not an additional process for watermarking, and adaptively applied as an assigned quantizer according to application area. In the embedding process, a LFSR(Linear feedback shift register) is used to hide the watermarking positions. Therefore the embedded watermark can be extracted by only the owner who knows the initial value of LFSR without the original image. The experimental results showed that the proposed algorithm satisfies the robustness and imperceptibility corresponding to the major requirement of watermarking.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.418-424
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• 2010

Many researchers studied methods for the generation of maximum length pseudo random sequences. Sabater et al. analyzed shrunken sequences which are effectively generated by SG(Shrinking Generator) using CA(Cellular Automata). In this paper we propose a new SG which is called LCSG(LFSR and CA based Shrinking Generator) using an LFSR with control register and CA with generator register. The proposed shrunken sequences generated by LCSG have longer periods and high complexities than the shrunken sequences generated by the known method. And we analyze the generated sequences using LCSG.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

In this paper, we proposed a blind watermarking algerian to use characteristics of a scalar quantizer which is the recommended in the JPEG2000 and JPEG. The proposed algorithm shifts a quantization index according to the value of each watermark bit to prevent losing the watermark information during the compression by quantization. Therefore, the watermark is embedded during the process of quantization, not an additional process for watermarking, and is adaptively applied as a assigned quantizer according application areas. Before embedding process, a LFSR(Linear feedback shift register) rearranged the watermark for the security of the watermark itself and in the embedding process, a LFSR is used to hide the watermarking positions. Therefore the embedded watermark can he extracted by only the owner who knows the initial value of LFSR without the original image. The visual recognizable pattern such as a binary image was used as the watermark. The experimental results showed that the proposed algerian satisfies the robustness and imperceptibility corresponding to the major requirement of watermarking. The results showed the largest error rate to be $5.7\%$ for attack. The experimental result which compares the proposed algorithm with the Mohamed algorithm showed that the proposed algorithm was better than it, exactly $4\~5$ times for the attacks of JPEG and JPEG2000.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2421-2429
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• 2000

With the advance of wireless communications technology, mobile communications have become more convenient than ever. Nowadays, people can communicate with each other on any place at any time. However, because of the openness of wireless communications, the way to protect the privacy between communicating parties is becoming a very important issue. In this paper, we present a study on the authentication and message encryption algorithm to support roaming service to the GSM network. To propose an authentication and message encryption algorithm applicable to the GSM system, the security architecture of the GSM outlined in the GSM standard is briefly introduced. In the proposed cryptosystems we use a new hash function for user authentication and a stream cipher based on Linear Feedback Shift Register(LFSR) for message encryption and decryption. Moreover, each algorithm is programmed with C language and simulated on IBM-PC system and we analyze the randomness properties of the proposed algorithms by using statistical tests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.137-145
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• 2003

Nowadays, people can communicate with each other on any time at my place by development of wireless communications. But, the openness of mobile communications Poses serious security threats and the security is necessary on mobile communications to support the secure communication channel. The most commonly method is stream cipher for mobile communications. Generally, this stream cipher is implemented by LFSR(Linear Feedback Shift Register). On this paper proposes the modified mechanism of the S box is usually used in block cipher to advance security og the stream cipher and this mechanism is the modified three one in consideration og the randomness. Generally, S box that is function with nonlinear property makes data more strong by attack. The randomness test of the proposed algorithm is used Ent Pseudorandom Number Sequence Test Program and by the test result it proves that it has better randomness and serial correlation value than the based stream cipher on respective test.