• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.10 no.1
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• pp.129-136
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• 1998

Pressure drop and heat transfer characteristics of a periodically fully developed flow in the flat channel with protrusions are investigated. The effects of shape and location of protrusion on the pressure drop and heat transfer are numerically analyzed in the present study. Taguchi method is used to optimize these parameters. It is found that the ratio of the height of protrusion to channel height shows larger influence on the pressure drop and heat transfer than the ratio of the length of protrusion to module length. As the height of protrusion increases, pressure drop and heat transfer increase, but if the height of protrusion exceeds 2/3 of the channel height, there is a substantial pressure drop. The results also show that the optimal length and height of protrusion are half of the module length and half of the channel height, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.897-900
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• 2005

RF linearity of double-gate MOSFETs is investigated using accurate two-dimensional simulations. The linearity has been analyzed using the Talyor series. Transconductance is dominant nonlinear source of CMOS. It is shown that DGMOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration. The minimum $P_{IP3}$ data are compared in each case. It is shown that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration..

• Journal of the Korean Society of Industry Convergence
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• v.24 no.6_1
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• pp.683-691
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• 2021

Bipolar plates with channel width of 0.5 mm, 0.4 mm, and 0.3 mm respectively were printed using a 3D printer. The shape of three b ipolar plates was rectangular, the channel depth was 0.5 mm, and the thickness of base was 0.5 mm. The bipolar plate with channel width of 0.5 mm had 45 channels, and their active area was 44.5 mm × 50 mm. The bipolar plate with channel width of 0.4 mm had 57 channels and its active area was 45.2 mm × 50 mm, and the bipolar plate with channel width of 0.3 mm had 75 channels and its active area was 44.7 mm × 50 mm. The bipolar plates were printed using PLA filament. The cross-sectional lengths of the bipolar plates with channel widths of 0.5 mm and 0.4 mm were identical by 96% of the designed cross-sectional length. Whereas the bipolar plate with a channel length of 0.3 mm had a large difference of 25% from the designed cross-sectional length.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1286-1293
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• 1988

A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.77-85
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• 1999

By assuming a linearly graded depletion edge approximation in the intrinsic MOS region and by taking into account the mobility variation dependent on both lateral and vertical fields, a physics-based analytical model for a short-channel(n-channel) MOSFET is suggested. Derived expressions for the threshold voltage and the drain current of typical MOSFET is structures could be used in a unified manner for all operating range. The threshold voltage was calculated by changing following variables : channel length, drain-source voltage, source-substrate voltage, p-substrate doping level, and oxide thickness. It is shown that the threshold voltage decreases almost exponentially as the channel length decreases. In addition, the short-channel threshold voltage roll-off, the channel length modulation and the electron mobility degradation can be derived within a satisfactory accuracy.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.