• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.142-147
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• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.1-8
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• 2002

C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• ETRI Journal
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• v.46 no.3
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• pp.392-403
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• 2024

Even though generalized frequency division multiplexing is an alternative waveform method expected to replace the orthogonal frequency division multiplexing in the future, its implementation must alleviate channel effects. Least-squares (LS), a low-complexity channel estimation technique, could be improved by using the discrete Fourier transform (DFT) without increasing complexity. Unlike the usage of the LS method, the DFT-based method requires the receiver to know the channel impulse response (CIR) length, which is unknown. This study introduces a simple, yet effective, CIR length estimator by utilizing LS estimation. As the cyclic prefix (CP) length is commonly set to be longer than the CIR length, it is possible to search through the first samples if CP is larger than a threshold set using the remaining samples. An adaptive scale is also designed to lower the error probability of the estimation, and a simple signal-to-interference-noise ratio estimation is also proposed by utilizing a sparse preamble to support the use of the scale. A software simulation is used to show the ability of the proposed system to estimate the CIR length. Due to shorter CIR length of rural area, the performance is slightly poorer compared to urban environment. Nevertheless, satisfactory performance is shown for both environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.1-6
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• 2004

For MOSFET devices with nanometer range gate length, accurate extraction of effective gate length is highly important because transistor characteristics become very sensitive to effective channel length. In this paper, we propose a new approach to extract the effective channel length of nanometer range MOSFET by Capacitance Voltage(C-V) method. The effective channel length is extracted using gate to source/drain capacitance( $C_{gsd}$). It is shown that 1/$\beta$ method, Terada method and other C-V method are inadequate to extract the accurate effective channel length. Therefore, the proposed method is highly effective for extraction of effective channel length of 100nm CMOSFETs.s.

• Journal of IKEEE
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• v.20 no.3
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• pp.330-332
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• 2016

In this study, we investigate the influence of channel length of bendable a-Si:H thin film transistors (TFTs) on their electrical characteristics as a function of bending strain. Under a tensile strain of 1.69%, $8{\mu}m$-channel-length TFT has the threshold voltage shift up to 5.25 V, while $100{\mu}m$-channel-length TFT operates stably.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.581-586
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• 2015

This paper has analyzed the variation of subthreshold swing for the ratio of channel length and thickness for asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factors to control the short channel effects increase since top and bottom gate structure can be fabricated differently. The degradation of transport property due to rapid increase of subthreshold swing can be specially reduced in the case of reduction of channel length. However, channel thickness has to be reduced for decrease of channel length from scaling theory. The ratio of channel length vs. thickness becomes the most important factor to determine subthreshold swing. To analyze hermeneutically subthreshold swing, the analytical potential distribution is derived from Poisson's equation, and conduction path and subthreshold swing are calculated for various channel length and thickness. As a result, we know conduction path and subthreshold swing are changed for the ratio of channel length vs. thickness.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1399-1404
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• 2015

This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10^-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.