• Title/Summary/Keyword: Latch up

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A Study on the Design of the LIGBT Structure with Trap Injection for Improved Electrical Characteristics (트랩 주입의 구조적 설계에 따른 LIGBT의 전기적 특성 개선에 관한 연구)

  • Choo, Kyo-Hyuck;Kang, Ey-Goo;Lee, Jung-Hoon;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.932-934
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    • 1999
  • In this paper, the new IGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The simulations are used in order to investigate the effects of the position, width and concentration of trap injection region using 2D device simulator MEDICI. And, their electrical characteristics are analyze and the optimum design parameters are extracted. As a result of simulation, the turn off time for the proposed LIGBT model A by the trap injection is $0.78{\mu}s$. And, the latch up voltage is 3.4V and forward blocking voltage is 168V which are superior to that of conventional structure. In addition, the proposed model is achieved more efficient in switching time and process effort. Therefore, It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

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Characteristic Study for Defect of Top Si and Buried Oxide Layer on the Bonded SOI Wafer (Bonded SOI wafer의 top Si과 buried oxide layer의 결함에 대한 연구)

  • Kim Suk-Goo;Paik Un-gyu;Park Jea-Gun
    • Korean Journal of Materials Research
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    • v.14 no.6
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    • pp.413-419
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    • 2004
  • Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

Implementation of Optimal Flicker Free Display Controller for LED Display System (LED 디스플레이 시스템을 위한 최적의 플리커 프리 디스플레이 제어장치 구현)

  • Lee, Juyeon;Kim, Daesoon;Lee, Jongha
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.123-133
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    • 2017
  • In this paper, we developed an optimal flicker-free control algorithm operating within 16 luminance implementation bits and 512 brightness implementation pulses irrespective of LPM(LED Pixel Matrix) module configuration on dynamic driving method of LED display system. As an implementation method, we turned the refresh rate up by increasing the number of scans through multiple shift-latches which were devised from conventional shift-latch scheme for full color representation. As a result, the LED display system of this method has no flicker phenomenon because of the novel refresh rate higher than 2,040[Hz] incomparable to 240~480[Hz] of conventional system.

Electrical Characteristics of 1,200 V Reverse Conducting-IGBT (1,200 V Reverse Conducting IGBT의 전기적 특성 분석)

  • Kim, Se Young;Ahn, Byoungsub;Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.3
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    • pp.177-180
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    • 2020
  • This paper focuses on the 1,200-V level reverse conducting-insulated gate bipolar transistor (RC-IGBT). The structure of the RC-IGBT has an n+ collector at the collector terminal. The breakdown voltage, Vth, Vce-sat, and turn-off time, and the electrical characteristics of a field-stop IGBT (FS-IGBT) and RC-IGBT are compared and analyzed using simulations. Based on the results, the RC-IGBT obtained a turn-off time of 320.6 ㎲ and a breakdown voltage of 1,720 V, while the FS-IGBT obtained a turn-off time of 742.2 ㎲ and a breakdown voltage of 1,440 V. Therefore, RC-IGBTs have faster on/off transitions and a higher breakdown voltage, which can reduce the size of the element.

High Current Behavior and Double Snapback Mechanism Analysis of Gate Grounded Extended Drain NMOS Device for ESD Protection Device Application of DDIC Chip (DDIC 칩의 정전기 보호 소자로 적용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘 분석)

  • Yang, Jun-Won;Kim, Hyung-Ho;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.2
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    • pp.36-43
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    • 2013
  • In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

Analysis of the electrical characteristics of SOI LIGBT with dual-epi layer (이중 에피층을 가지는 SOI LIGBT의 전기적 특성분석)

  • Kim, Hyoung-Woo;Kim, Sang-Cheol;Kim, Ki-Hyun;Kim, Eun-Dong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.288-291
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    • 2004
  • Due to the charge compensation effect, SOI(Silicon-On-Insulator) LIGBT with dual-epi layer have been found to exhibit both low forward voltage drop and high static breakdown voltage. In this paper, electrical characteristics of the SOI LIGBT with dual-epi structure is presented. Trenched anode structure is employed to obtain uniform current flowlines and shorted anode structure also employed to prevent the fast latch-up. Latching current density of the proposed LIGBT with $T_1=T_2=2.5{\mu}m,\;N_1=7{\times}10^{15}/cm^3,\;N_2=3{\times}10^{15}/cm^3$ is $800A/cm^2$ and breakdown voltage is 125V while latching current density and breakdown voltage of the conventional LIGBT is $700A/cm^2$ and 55V.

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Radiation testing of low cost, commercial off the shelf microcontroller board

  • Fried, Tomas;Di Buono, Antonio;Cheneler, David;Cockbain, Neil;Dodds, Jonathan M.;Green, Peter R.;Lennox, Barry;Taylor, C. James;Monk, Stephen D.
    • Nuclear Engineering and Technology
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    • v.53 no.10
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    • pp.3335-3343
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    • 2021
  • The impact of gamma radiation on a commercial off the shelf microcontroller board has been investigated. Three different tests have been performed to ascertain the radiation tolerance of the device from a nuclear decommissioning deployment perspective. The first test analyses the effect of radiation on the output voltage of the on-board voltage regulator during irradiation. The second test evaluated the effect of gamma radiation on the voltage characteristics of analogue and digital inputs and outputs. The final test analyses the functionality of the microcontroller when using an external, shielded voltage regulator instead of the on-board voltage regulator. The results suggest that a series of latch-ups occurs in the microcontroller during irradiation, causing increased current drain which can damage the voltage regulator if it does not have short-circuit protection. The analogue to digital conversion functionality appears to be more sensitive to gamma radiation than digital and analogue output functionality. Using an external, shielded voltage regulator can prove beneficial when used for certain applications. The collected data suggests that detaching the voltage regulator can extend the lifespan of the platform up to approximately 350 Gy.

A study on the Design of NPN BJT built-in SCR for Low Voltage Class ESD Protection (저전압급 ESD 보호를 위한 NPN BJT 내장형 SCR 설계에 관한 연구)

  • Jeong, Seung-Gu;Baek, Seung-Hwan;Lee, Byung-Seok;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.26 no.3
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    • pp.520-523
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    • 2022
  • In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.

TID and SEL Testing on PWM-IC Controller of DC/DC Power Buck Converter (DC/DC 강압컨버터의 PWM-IC 제어기의 TID 및 SEL 실험)

  • Lho, Young Hwan;Hwang, Eui Sung;Jeong, Jae-Seong;Han, Changwoon
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.41 no.1
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    • pp.79-84
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    • 2013
  • DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a PWM-IC (pulse width modulation-integrated circuit) controller, a MOSFET (metal-oxide semiconductor field effect transistor), inductor, capacitor, etc. It is shown that the variation of threshold voltage and the offset voltage in the electrical characteristics of PWM-IC increase by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 4 heavy ions applied for SEL (Single Event Latch-up) make the PWM pulse unstable. Also, the output waveform for the given input in the DC/DC converter is observed by the simulation program with integrated circuit emphasis (SPICE). TID testing on PWM-IC is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the PWM operation is studied at SEL testing after implementation of the controller board.

Ultra-Power-Saving 2 Ports PLC Wall Switch Development (초절전형 PLC 2구 스위치 개발)

  • Han, Jae-Yong;Lee, Sun-Heum
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.51-55
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    • 2007
  • Generally, PLC (Power Line Communication) based home automation devices such as wall switch, walt socket, gas controller, etc, must maintain wake-up status at all time to control other electronic devices and monitor their on/off status whether they are in service or not. In order to reduce the unnecessary energy consumption during the standby mode, the new power-saving PLC 2 ports wall switch has been developed, separating PLC communication part and controller part and introducing sleep mode. In addition, to expand life cycle of PLC product and to reduce the rate of product failure in active mode, the instant controlling method in controlling process is adopted instead of the maintenance controlling method. In comparison to the earlier model, the new 2 ports PLC wall switch has reduced power by 0.95[W] less in standby mode and 3.2[W] less in active mode than the previous one.