• 대한전자공학회논문지
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• 제26권4호
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• pp.67-72
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• 1989

부분산화공정(LOCOS : local oxidation of silicon)에서 발생하는 새부리의 길이를 줄이기 위하여 상온 플라즈마 질화막을 잉요한 시로운 공정에 대해 연구하였다. 400W, 100kHz의 교류 전력에 의한 질소 플라즈마로 실리콘 위에 두께가 $100{\AA}$ 미만의 균일한 실리콘 질화막을 형성시킬 수 있었다. 이렇게 형성된 질화막은 실리콘을 4000${\AA}$두께로 산화시키는 공정에서 실리콘의 산화를 효과적으로 방지할 수 있었고 새부리의 길이를 0.2${mu}m$로 감소시킬 수 있다는 것을 SEM 단면도로 확인하였다. 이 길이는 두꺼운 LPCVD 질화막을 이용한 기존의 부분산화공정에서의 0.7${mu}m$ 보다 훨씬 줄어든 것이다. Secco에칭 후 SCM으로 단면을 보았을때 새부리 근처에서 결정 결함을 관찰할 수 없었다. 이 새로운 LOCOS공정으로 $N^+/P^-\;well,\;P^+/N^-$ well 다이오드를 만들어 누설전류를 측정하였다. 그 결과 기존의 LOCOS 공정에 의한 성질보다 우수하거나 동등한 성질을 나타내었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.429-432
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• 1987

A new LOCOS (Local Oxidation of Silicon) process using a thin nitride film directly deposited on the silicon substrate by LPCVD has been developed in order to reduce the bird's beak length. SEM studies showed that nitride thickness of 50nm can decrease the bird's beak length down to 0.2um with 450nm field oxide. No crystalline defects are observed around the bird's beak after the Wright etch. A 30% improvement in current density was obtained when this new method was applied to MOS transistors (W/L*2.9/20.4) compared to conventional LOCOS process (bird's beak length=0.7um). Other various electrical parameters improved by this new simple LOCOS process are reported in this paper.

• 전자공학회논문지A
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• 제31A권12호
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.38-42
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• 1999

Using the LOCOS process, we have fabricated the lateral type polysilicon field emission triodes with poly-Si/oxide/Si structure and investigated their current-voltage characteristics for three biasing modes of operation. The fabricated devices exhibit excellent electrical performances such as a relatively low turn-on anode voltage of 14 V at VGC = 0V, a stable and high emission current of 92${\mu}$A/triode over 90 hours, a small gate leakage current of 0.23 ${\mu}$A/triode and an outstanding transconductance of 57${\mu}$S/5triodes at VGC = 5V and VAC = 26V. these superior electrical operation is believed to be due to a large field enhancement effect, which is related to the sharp cathode tips produced by the LOCOS process as well as the high aspect ratio (height /radius ) of the cathode tip end.

• 전자공학회논문지A
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• 제29A권11호
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• pp.91-96
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• 1992

The technology of LOCOS(LOCal Oxidation of Silicon) was used to form the island of SOI film. After this, the SOI film was recrystallized by CO$_2$ laser and metal gate nMOSFETs were fabricated on this SOI film and their electrical characteristics were measured. The kink effect was not nearly observed and edge channel effect was found in the SOI nMOSFETs. The threshold voltage was about 0.5V, the electron mobility was about 340cm$^2$V$\cdot$S and an ON/OFF ratio above 10$^{5}$ was obtained at V_{DS}$=4V. The electrical characteristics were improved by laser recrystallization.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.544-547
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• 2007

본 연구에서는 Shallow trench isolation(STI)를 형성하기 위한 과정을 제시할 것이다. 소자간 분리를 위한 전통적인 방법으로 LOCOS(Local Oxidation of Silicon) 방식이 사용되어왔으나, 소자가 미세해짐에 따라 LOCOS 방식에서 나타나는 단차와 Birds Beak이라는 횡 방향의 산화에 의한 활성 영역의 손실을 무시할 수 없게 되어 새로운 소자 분리 방법이 필요하게 되었으며 이러한 요구에 의해 도입된 Isolation 기술이 Shallow Trench Isolation(STI) 기술이다. 다양한 etching options은 중요한 부분이다. 이 경우에 trench etching의 방향은 점점 좁아지는 측면을 경사지게 하면서 협곡을 만드는 효과적인 방법을 사용할 것이다. 본 연구에서는 좁은 협곡(Shallow trench)의 절반만 시뮬레이션 될 것이다. 만약 모든 협곡의 시뮬레이션을 필요로 한다면 다변의 etching은 사용될 수 있다. STI 공정의 핵심은 trench etch를 좁게하면서 반도체 소자를 어떻게 하면 잘 분리할 수 있는가에 있다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.93-101
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• 2002

We have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of $300{\;}\bu\textrm{A}/tip$ at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing $Si_3N_4$ film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for $7\bu\textrm{m}$ gap and an emission current of~580 nA/l0tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.

• Journal of Information Display
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• 제2권3호
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• pp.60-65
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• 2001

Lateral type poly-silicon field emitters were fabricated by utilizing the LOCOS (Local Oxidation of Silicon) process. For the implementation 'of an ideal field emission device with quasi-zero tunneling barrier, a new and fundamental approach has used conducted by introducing an intelligent carbon-based thin layer on the cathode tip surface via a field-assisted self-aligning of carbon (FASAC) process. Fundamental lowering of the turn-on field for the electron emission was feasible through the control of both the tip shape and surface barrier height.

• ETRI Journal
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• 제27권5호
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.