• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5A
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• pp.311-316
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• 2012

In this paper, a bit-mapping scheme is proposed for partial Chase combining in LDPC-coded systems. Contrary to the previously known bit mapping that assigns the information bits to more reliable channels, the proposed mapping assigns the codeword bits of irregular LDPC codes to distinct Gaussian channels by considering the characteristics of LDPC codes and channels. The recursion equation for partial Chase combining is derived by using the density evolution technique, based on it, the best bit mapping among the various bit-mapping schemes is derived, and the validity of them is confirmed through simulation.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.189-192
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• 2002

최근 인터넷과 노트북, 그리고 휴대용 이동 통신 기기들이 급속히 보급되면서 사용자들은 일반 컴퓨팅 환경보다 편리한 이동성과 대용량의 데이터 전송을 요구하고 있다. 따라서, 본 논문에서는 이러한 요구에 부응하기 위하여 LDPC coding 기술 및 등화기술을 OFDM 방식에 적용한 차세대 무선 시스템을 제안한다.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.123-123
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• 2004

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.436-444
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• 2005

Unitary matrix modulation (UMM) is investigated in multiple antennas system that is called unitary space-time modulation (USTM). In an OFDM, the diagonal components of UMM with splitting over the coherence bandwidth (UMM-S/OFDM) have been proposed. Recently LDPC code is strongly attended and studied due to simple decoding property with good error correction property. In this paper, we propose LDPC coded UMM-S/OFDM for increasing the system performance. Our proposed system can obtain frequency diversity using UMM-S/OFDM like USTM/OFDM, and large coding gain using LDPC code. The superior characteristics of the proposed UMM-S/OFDM are demonstrated by extensive computer simulations in multi-path Rayleigh fading channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.229-232
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• 2012

This paper describes performance evaluation using fixed-point Matlab modeling and simulation, and hardware design of LDPC decoder which is based on Improved Normalized Min-Sum(INMS) decoding algorithm. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard. Considering hardware complexity, it is designed using a block-serial(partially parallel) architecture which is based on layered decoding scheme. A DFU based on sign-magnitude arithmetic is adopted to minimize hardware area. Hardware design is optimized by using INMS decoding algorithm whose performance is better than min-sum algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.92-96
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• 2008

Practical communication systems need to operate at various different rates. This paper describes and analyzes low-density parity check codes for various different rates. From a specific mother code, it allows LDPC codes for different rate. The advantage of this technique is that each different rate LDPC codes have a same block length as mother code though the rate changes so it can make up for the weak points of puncturing and shortening which reduce their block length as the rate changes. Row-splitting method is to split the row, so that the rate changes from a higher rate to lower rate and cause of its own property, it can overcome the defect of row-combining method.