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http://dx.doi.org/10.5573/ieie.2014.51.10.072

Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture  

Ajaz, Sabooh (Department of Information and Communication Engineering, Inha University)
Lee, Hanho (Department of Information and Communication Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.10, 2014 , pp. 72-79 More about this Journal
Abstract
This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.
Keywords
Low-density-parity-check (LDPC); min-sum decoder; pipeline-aware; forward error correction (FEC);
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1 C. Wey, M. Shieh, S. Lin, "Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation", IEEE Trans. Circuits Syst. I, vol.55, no. 11, pp. 3430-3437, Dec. 2008.   DOI   ScienceOn
2 M. Mansour and N. Shanbhag, "High-throughput LDPC decoders," IEEE Trans. VLSI Systems, vol. 11, no. 6, pp. 976-996, Dec. 2003.   DOI   ScienceOn
3 Z. Cui, Z. Wang, Y. Liu, "High-throughput layered LDPC decoding architecture," IEEE Trans. VLSI Systems, vol. 17, no. 4, pp. 582-587, Apr. 2009.   DOI   ScienceOn
4 J. Zhang, M Fossorier, "Shuffled Iterative Decoding", IEEE Trans. on Comm., vol. 53, no. 2, pp. 209-213, Feb. 2005.   DOI   ScienceOn
5 D. Oh, K. Parhi, "Min-Sum decoder architecture with reduced word length for LDPC Codes", IEEE Trans. Circuits Syst. I, vol. 57, no. 1, pp. 105-115, Jan. 2010.   DOI
6 S. Kim, G. E. Sobelman, H. Lee "A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes," IEEE Trans. on VLSI Systems, vol. 19, no. 6, pp. 1099-1103, Jun. 2011.   DOI   ScienceOn
7 L. Liu and C.-J. R. Shi, "Sliced message passing: High throughput over-lapped decoding of high-rate low-density parity-check codes," IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3697-3710, Nov. 2008.   DOI   ScienceOn
8 H. Lee, S. Ajaz, "A High-Throughput QC-LDPC Decoder Architecture for Multi-Gigabit WPAN Systems," Journal of The Institute of Electronics Engineers of Korea Vol. 50, No. 2, pp. 105-113, Feb. 2013.   과학기술학회마을   DOI   ScienceOn
9 L. Gianluigi, S. Song, L. Lan, Y. Zhang, S. Lin and W.E Ryan "Design of LDPC Codes: A Survey and New Results", J. of Communication Software and Systems, vol. 2, pp. 191-211, Sep. 2006.
10 Y. Zhang, W.E. Ryan, "Structured IRA Codes: Performance Analysis and Construction", IEEE Trans. on Comm., vol. 55, no. 5, pp. 837-844, May 2007.   DOI   ScienceOn
11 A. Darabiha,, A. C. Carusone,, F. R. Kschischang, "Block-Interlaced LDPC Decoders with Reduced Interconnect Complexity", IEEE Trans. Circuits Syst. II, Express Brief, vol.55, no. 1, pp. 74-78, Jan. 2008.   DOI   ScienceOn
12 K. Zhang, X. Huang, Z. Wang, "High-throughput layered decoder implementation for quasi-cyclic LDPC codes", IEEE J. on Sel. Areas in Comm., vol. 27, no. 6, pp. 985-994, Aug. 2009.   DOI   ScienceOn
13 Y. Sun and J. R. Cavallaro, "A low power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards," IEEE International SOC Conference, pp. 367-370, Sept. 2008.
14 C. Roth, P. Meinerzhagen, C. Studer. and A. Burg, "A 15.8 pJ/bit/iter Quasi-Cyclic LDPC Decoder for IEEE 802.11n in 90 nm CMOS," IEEE Asian Solid State Circuits Conference, pp. 1-4, Nov. 2010.
15 M. M. Mansour and N. R. Shanbhag, "A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip," IEEE Journal of Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.   DOI   ScienceOn
16 J. R. Hauser, "Handbook of Semiconductor Manufacturing Technology," editor R. Doering and Y. Nishi, CRC Press, Bosa Roca, 2007, 2nd ed. 1-21.