• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.4
• /
• pp.65-71
• /
• 2007

Doherty amplifier has more efficiency and distortion than general amplifier. These distortion classified amplitude distortion and phase distortion, memory effect distortion. This paper reports on an attempt to investigate, model and quantity the contribution of the electrical nonlinearity effects and the thermal memory effects to a doherty amplifier's distortion generation and suggests thermal memory effect compensator for pre-distorter. Also this paper reports on the development of an accurate dynamic expression of the instantaneous junction temperature as a function of the instantaneous dissipated power. The parameters of suggested model suppress thermal memory effects doherty amplifier with pre-distorter. Pre-distorter with electrothermal memory effect compensator for doherty amplifier enhanced ACLR performance about 22 dB than general doherty amplifier. Experiment results were mesured by 50W LDMOS Doherty amplifier and pre-distorter with electrothermal memory effect compensator was simulated by ADS.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.13-18
• /
• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.10
• /
• pp.1-6
• /
• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.9 s.339
• /
• pp.49-56
• /
• 2005

Memory effect, which influence the performance of Doherty amplifier, become more significant and critical in designing these circuits as the modulation signal bandwidth and operation power level increase. This paper reports on an attempt to investigate, model and quantity the contribution of the electrical nonlinearity effects and the thermal memory effects to a Doherty amplifier's distortion generation. Also this raper reports on the development of an accurate dynamic expression of the instantaneous junction temperature as a function of the instantaneous dissipated power. This expression has been used in the construction of an electrothermal model for the Doherty amplifier. Parameters for the nelv proposed behavior model were determined from the Doherty amplifier measurements obtained under different excitation conditions. This study led us to conclude that the effects of the transistor self-heating phenomenon are important for signals with wideband modulation bandwidth(ex. W-CDMA or UMTS signal). Doherty amplifier with electrothermal memory effect compensator enhanced ACLR performance about 20 dB than without electrothemal memory effect compensator. Experiment results were mesured by 60W LDMOS Doherty amplifier and electrothermal memory effect compensator was simulated by ADS.

• Journal of Navigation and Port Research
• /
• v.30 no.5 s.111
• /
• pp.351-356
• /
• 2006

In this paper, the high efficiency Doherty power amplifier has been designed and realized for microwave applications. The Doherty amplifier has been implemented using silicon MRF 281 LDMOS FET. The RF performances cf the Doherty power amplifier (a combination of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class AB amplifier alone. The realized Doherty power amplifier P1dB output power has 33dBm at 2.3GHz frequency. Also the Doherty power amplifier shows 11dB gain and -17.8dB input return loss at 2.3GHz to 2.4GHz. The designed Doherty amplifier has been improved the average PAE by 10% higher efficiency than a class AB amplifier alone. The Maximum PAE of designed Doherty power amplifier has been 39%.

• Journal of Advanced Navigation Technology
• /
• v.27 no.6
• /
• pp.849-854
• /
• 2023

In this paper, a high-efficiency power amplifier was designed by applying the operating point Class J using LDMOS(laterally diffused metal oxide semiconductor) and optimizing the output matching circuit so that the second harmonic impedance becomes the reactance impedance. The designed power amplifier has a frequency of 108 ~ 110 MHz, Characteristics of PAE(power added efficiency) is 71.5% at P_SAT output (54.5 dBm), 55.5% at P_1dB output (51.5 dBm), and 24.38% at 45 dBm. The CSB(carrier with sideband) amplifier, which is the reference signal in the spatial modulation method, has an operating output of 45 dBm ~ 35 dBm, and linear SDM(sum in the depth of modulation) characteristics(40% ± 0.3%) were obtained. We measure the characteristics in amplitude modulation according to the bias operating point of the power amplifier for CSB and propose the optimal operating point to obtain linear modulation characteristics.

• ETRI Journal
• /
• v.25 no.3
• /
• pp.195-202
• /
• 2003

This paper proposes a new LDMOSFET structure with a trenched sinker for high-power RF amplifiers. Using a low-temperature, deep-trench technology, we succeeded in drastically shrinking the sinker area to one-third the size of the conventional diffusion-type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power-added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below -40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.

• Proceedings of the KIEE Conference
• /
• 2001.11a
• /
• pp.146-148
• /
• 2001

LIGBT의 캐소드에 전류 제한 능력이 있는 LDMOS를 직렬 연결하여 LIGBT의 전류가 기생 사이리스터가 동작하게 되는 지점까지 증가하는 것을 억제함으로써 기생 사이리스터의 동작으로 인한 LIGBT의 불안정 동작 효과적으로 방지하는 새로운 구조의 LIGBT를 제안한다. 또한 턴-오프 시에 LDMOS의 전류 차단 능력에 의해 전류가 기존의 소자에 비해 빠르게 감소하는 효과로 인해 빠른 스위칭 속도를 얻을 수 있었다.

• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.19-22
• /
• 2004

This paper implemented 2.14GHz band Adaptive Hybrid Doherty (AHD) amplifier, as well as, wished to improve the high power characteristics and efficiency by composing bias adjustment circuit with LDMOS. Finally, through CAE, confirmed that AHD amplifier have superior performance than hybrid balanced amplifier. Superior characteristics of AHD amplifier is expected to affect immensely in amplifier field hereafter.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.8
• /
• pp.38-43
• /
• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.