• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1606-1608
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• 1996

An the SOI RESURF LDMOS with a taper oxide on the drain is proposed and verified by the device simulator, MEDICI. Simulation results on the proposed LDMOS exhibits the increase in the breakdown voltage by 12 % and reduction in the drift region length by 25 %.

• 전기학회논문지
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• 제61권12호
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• pp.1872-1876
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• 2012

A calculation method of the breakdown voltage for the drain region with the cylindrical structure in LDMOS is proposed. The depletion region of the drain is divided into many smaller regions and the doping concentration of each split region is assumed to be uniformly distributed. The field and potential in each split region is calculated by the integration of the Poisson equation and the ionization integral method is used to compute the breakdown voltage. The breakdown voltage resulted from the proposed method shows the maximum relative error of 2.2% compared with the result of the 2-dimensional device simulation using BANDIS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 하계종합학술발표회논문초록집
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• pp.315-315
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• 2004

• 전기전자학회논문지
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• 제15권1호
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• pp.37-42
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• 2011

본 논문에서는 0.35 um BCD 공정을 통한 고내압 BCD 소자와 새로운 구조의 BCD 소자를 제작하여 전기적 특성을 분석하였다. 20 V급 BJT 소자, 30/60 V급 HV-CMOS, 40/60 V급 LDMOS 소자의 전기적 특성을 분석하고, 동일 공정을 통해 높은 전류 이득을 갖는 수직/수평형 NPN BJT와 고내압 특성의 LIGBT 소자를 제안하였다. 제안된 수직/수평형 NPN BJT의 항복전압은 15 V, 전류이득은 100으로 측정되었으며, 고내압 특성의 LIGBT의 항복전압은 195 V, 문턱전압은 1.5 V, Vce,sat은 1.65 V로 측정 되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.673-681
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• 2014

In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped $P^+$ region which is connected to the P-top layer in the drift region. The $P^+$ region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel $P^+P$-top device also present cost efficiency due to the fact that the $P^+$ region can be fabricated together with the P-type body contact region without any additional mask.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 한국전자파학회논문지
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• 제29권2호
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• pp.99-108
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• 2018

본 논문은 마그네트론 대체를 위한 반도체 전력 발진기 모듈 설계에 관련된 내용을 기술하였다. 300급 LDMOS 단일 전력 증폭기의 특성을 확인하였고 두 개를 결합하여 모듈을 구성하였다. 결합된 모듈에 delay-line feedback loop을 구성하고 위상 천이기를 이용하여 위상을 조절하여 발진기를 구동시켰다. 발진기 모듈 측정 결과 주파수 2.327 GHz에서 출력 800 W, 효율 58 %로 측정되었다. 이 결과는 시뮬레이션 결과와 유사한 특성을 보여준다.

• 한국항해항만학회지
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• 제27권1호
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• pp.81-86
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• 2003

본 논문은 초고주파 전력증폭기용 LDMOS(Lateral double-diffused MOS) MRF-21060소자의 게이트 바이어스 전압을 조절하여 온도 변화에 따른 드레인(Drain) 전류의 변화를 억제하기 위한 PNP 트랜지스터를 사용하여 능도 바이어스 회로 구현하였다. MRF-21060을 구동하기 위한 방법으로서는 AH1과 평형증폭기인 A11을 사용하여 구동 증폭단을 설계.제작하였다. 제작된 5W 초고주파 전력증폭기는 0~$60^{\circ}C$까지의 온도변화에 대하여 소모전류 변화량이 수동 바이어스 회로에서 0.5A로 높은 반면, 능동 바이어스 회로에서는 0.1A이하의 우수한 특성을 얻었다. 전력증폭기는 2.11~2.17GHz주파수 대역에서 32dB 이상의 이득과 $\pm$0.09dB이하의 이득 평탄도가 나타났으며, -19dB이하의 입.출력 반사손실을 가진다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.261-264
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• 2004

In this paper, we identify the memory effect of high power(125W) laterally diffused metal oxide-semiconductor(LDMOS) RF Power Amplifier(PA) by two tone IMD measurement. We measure two tone IMD by changing the tone spacing and the power level. Different asymmetric IMD is founded at different center frequency measurements. We propose the Tapped Delay Line-Neural Network(TDNN) technique as the modeling method of LDMOS PA based on two tone IMD data. TDNN's modeling accuracy is highly reasonable compared to the memoryless adaptive modeling method.