• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of Information Display
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• v.8 no.4
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• pp.15-18
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• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• ETRI Journal
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• v.14 no.3
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• pp.75-96
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• 1992

이중 매몰층, $1.5\mum$ 에피두께, 이중 well, LOCOS 소자격리, LDD MOS 소자와 이중 다결정실리콘 전극을 갖는 바이폴라 소자에 의하여 구성된 BiCMOS 소자를 제작하였다. 제작된 소자를 측정 및 분석한 결과, 31단 CML 바이폴라($A_E=2X8\mum^2$)링 발진기와 31단 CMOS( $A_E=1.25X5\mum^2$) 인버터 링 발진기로부터 94ps/5V 와 330ps/12V의 게이트 전달 지연시간/소자 강복전압을 갖는 바이폴라 및 MOS소자특성을 얻을 수 있었다. 또한 BiCMOS 소자의 경우, 31단 BiCMOS 링 발진기로부터 약 700ps의 게이트 전달 지연시간을 얻었으며, 출력부하의 증가에 따른 속도의 감속비가 완만한 전기적 특성을 얻을 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.16-19
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• 2007

In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analyzed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2153-2155
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• 2000

The not an organization a branch stream the maintenance factor class on a class and the roadway type for roadway lighting design, the facted an insufficiency maintenance factor to apply our the country conditions. The consideration of maintenance factors is not being fully applied for roadway lighting design in Korea. This paper consider optical characteristics and maintenance factors as well as LID of Luminaires in designing roadway lighting. Consideration of maintenance factors that are neme specified according to LDD(Luminaire Dirt Depreciation), LLD(Lamp Lumen Depreciation), AADT(Average Annual Daily Traffic) based on IESNA regulation. The analyzed optical characteristics are applied for stagger and cross roadway types with maintenance factors in the range of 0.51$\sim$1.00 and equipment factor of 0.9.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.50-57
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• 2022

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.162-162
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• 1999

초고주파 집적회로의 핵심소자로 각광을 받고 있는 GaAs MESFET(MEtal-emiconductor)은 게이트 형성 공정이 가장 중요하며, WNx 내화금속을 이용한 planar 게이트 구조의 경우 임계전압(Vth:threshold voltage)의 균일도가 우수할 뿐만 아니라 특히 Side-wall을 이용한 self-align 게이트는 소오스 저항을 줄일 수 있어 고성능의 소자 제작을 가능하게 한다.(1) 본 연구의 핵심이 되는 Side-wall을 형성하기 위하여 PECVD법에 의한 SiOx 박막을 증착하고, 건식식각법을 이용하여 SiOx side-wall을 형성하였다. 이 공정을 이용하여 소오스 저항이 낮고 임계전압의 균일도가 우수한 고성능의 self-aligned gate MESFET을 제작하였다. 3inch GaAs 기판상에 이온주입법에 의한 채널 형성, d.c. 스퍼터링법에 의한 WNx 증착, PECVD법에 의한 SiOx 증착, MERIE(Magnetic Enhanced Reactive Ion Etcing)에 의한 Side-wall 형성, LDD(Lightly Doped Drain)와 N+ 이온주입, 그리고 RTA(Rapid Thermal Annealing)를 사용하여 활성화 공정을 수행하였다. 채널은 40keV, 4312/cm2로, LDD는 50keV, 8e12/cm2로 이온주입하였고, 4000A의 SiOx를 증착한 후 2500A의 Side-wall을 형성하였다. 옴익 접촉은 AuGe/Ni/Au 합금을 이용하였고, 소자의 최종 Passivation은 SiNx 박막을 이용하였다. 제작된 소자의 전기적 특성은 hp4145B parameter analyzer를 이용한 전압-전류 측정을 통하여 평가하였다. Side-wall 형성은 0.3$\mu\textrm{m}$ 이상의 패턴크기에서 수직으로 잘 형성되었고, 본 연궁에서는 게이트 길이가 0.5$\mu\textrm{m}$인 MESFET을 제작하였다. d.c. 특성 측정 결과 Vds=2.0V에서 임계전압은 -0.78V, 트랜스컨덕턴스는 354mS/mm, 그리고 포화전류는 171mA/mm로 평가되었다. 특히 본 연구에서 개발된 트랜지스터의 게이트 전압 변화에 따른 균일한 트랜스 컨덕턴스의 특성은 RF 소자로 사용할 때 마이크로 웨이브의 왜곡특성을 없애주기 때문에 균일한 신호의 전달을 가능하게 한다. 0.5$\mu\textrm{m}$$\times$100$\mu\textrm{m}$ 게이트 MESFET을 이용한 S-parameter 측정과 Curve fitting 으로부터 차단주파수 fT는 40GHz 이상으로 평가되었고, 특히 균일한 트랜스컨덕턴스의 경향과 함께 차단주파수 역시 게이트 바이어스, 즉 소오스-드레스인 전류의 변화에 따라 균일한 값을 보였다. 본 연구에서 개발된 Side-wall 공정은 게이트 길이가 0.3$\mu\textrm{m}$까지 작은 경우에도 사용가능하며, WNx self-align gate MEESFET은 낮은 소오스저항, 균일한 임계전압 특성, 그리고 높고 균일한 트랜스 컨덕턴스 특성으로 HHP(Hend-Held Phone) 및 PCS(Personal communication System)와 같은 이동 통신용 단말기의 MMICs(Monolithic Microwave Integrates Circuits)의 제작에 활용될 것으로 기대된다.