• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• 대한전자공학회논문지
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• 제27권11호
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• pp.49-54
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• 1990

본 논문에서는 LDD(lightly doped drain)구조를 갖는 짧은 채널 MOSFET에서의 기생저항의 게이트 전압 의존도에 대한 모형을 제시하였다. 게이트 전극 밑에 위치한 LDD 영역에서는 게이트 전압에 의해 준 이차원적인 축적층(quasi two-dimensional accumulation layer)이 형성된다. 소오스 측 LDD 기생저항을 축적층의 저항과 벌크 LDD 저항의 병렬 연결로 취급하였으며 별크 LDD 저항은 채널의 반전층 끝으로부터 ${n^+}$영역의 경계까지 퍼짐 저항으로 근사하였다. 그리고 접합에서의 도우핑 농도 구배가 LDD 저항에 미치는 영향이 토의하였다. 본 모형의 결과로 선형 영역에서는 LDD 저항이 게이트 전압의 증가에 따라 감소하고, 포화영역에서는 채널과 LDD에서 속도포화를 고려한 결과, 게이트 전압에 대해 준 일차적으로 증가하는 것으나 나타나 발표된 실험결과들과 일치하였다.

• 전자공학회논문지A
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• 제33A권10호
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• 대한전자공학회논문지
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• 제24권3호
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• pp.478-485
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• 1987

Optimization of the sub-micron N-channel MOSFET with the LDD(Lightly Doped Drain)structure has been investigated. LDD devices with various length of n-region, n-dose and n-implantation species were fabricated for this purpose. It will be shown that LDD devices have lower substrate current by an order of magnitude and higher breakdown voltage than the conventional devices with comparable channel length. Optimized LDD structure has been found when the sidewall thickness is 2500\ulcorner and n-region is phosphorus implantd with the dose of 1.0E13/cm\ulcorner It has been found that transconductance degradation is less than 20%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1475-1477
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• 1997

We have fabricated a novel LDD structured polysilicon thin film transistor with a simple fabrication process, compared with the conventional LDD poly-Si TFT, without LDD implantation by employing taper etched $SiO_2$ film instead of LDD implant mask. The leakage current of the novel LDD device is reduced significantly in OFF state while keeping the ON current to be almost identical to that of the non-LDD poly-Si TFTs.

• 한국전기전자재료학회논문지
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• 제11권7호
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• pp.522-526
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• 1998

We have fabricated a LDD structured polysilicon thin film transistor with low leakge current and the optimized LDD length has been obtained. The device performance is improved is improved by hydrogen passivation process. The on.off current ratio of poly0Si TFT s with $0.5{\mu}m$ and $1.0{\mu}m$ LDD length is much higher than that of conventional structured device due to the decrease of leakege current. The optimized LDD length may be $0.5{\mu}$ from the experimental data such as on/off current ratio, threshold voltage and hydrogenation effect.

• 대한전자공학회논문지TE
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• 제37권2호
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• pp.12-16
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• 2000

본 연구는 n-채널 다결정 실리콘 박막 트랜지스터를 LDD 길이에 변화를 주며 제조한 후 이에 따른 전기적인 특성을 분석하였다. LDD 구조를 갖는 소자는 LDD 영역에 의한 직렬저항 효과와 드레인 부근의 전계 감소 효과에 의해서 기존의 구조를 가지는 소자에서 볼 수 있었던 Kink 현상이 사라지게 된다. 또한, on전류의 소폭 감소와 함께 큰 폭의 off 전류 감소가 일어나 on/off 전류비가 기존 구조를 갖는 소자보다 크게 증가하게 된다. 이는 LDD 영역에 의한 직렬저항 효과보다 전계 감소 효과가 더 지배적으로 나타나기 때문으로 사료된다.

• 전자공학회논문지A
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• 제32A권2호
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• pp.324-331
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• 1995

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• 대한전자공학회논문지
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• 제27권1호
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• pp.74-80
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• 1990

The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.