• The Korean Journal of Nuclear Medicine Technology
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• v.17 no.1
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• pp.71-75
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• 2013

Purpose: Currently, decrement revision using LDCT is used in PET/CT. But cold artifacts are often found in decrement revision image by mismatch between LDCT image and Emission image near diaphragm due to patient's respiration. This research studied reduction of cold artifact by patient's respiration using CTAC Shift among revision methods. Materials and Methods: From March to September in 2012, 30 patients who had cold artifacts by respiration were targeted using PET/CT Discovery 600 (GE Healthcare, MI, USA) equipment. Patients with cold artifacts were additionally scan in diaphragm area, and the image shown cold artifacts at whole body test were revised using CTAC Shift. Cold artifacts including image, additional scan image and CTAC Shift revision image were evaluated as 1~5 points with naked eye by one nuclear medicine expert, 4 radiotechnologists with over 5 year experience. Also, standard uptake value of 3 images was compared using paired t-test. Results: Additional scan image and CTAC Shift revision image received relatively higher score in naked eye evaluation than cold artifacts including image. The additional scan image and CTAC Shift revision image had high correlation as the results of ANOVA test of standard uptake value and did not show significant difference. Conclusion: When cold artifacts are appeared by patient's respiration at PET/CT, it causes not only patient inconvenience but troubles in test schedule due to extra radiation exposure and time consumption by additional scan. But if CTAC Shift revision image can be acquired with out additional scan, it is considered to be helped in exact diagnosis without unnecessary extra radiation exposure and additional scan.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Korean Journal of Optics and Photonics
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• v.18 no.6
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• pp.452-460
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• 2007

Ultra-low loss ZERODUR and fused silica mirrors were manufactured and their light scattering characteristics were investigated. For this purpose, ZERODUR and fused silica substrates were super-polished by the bowl feed method. The surface roughness were 0.292 ${\AA}$ and 0.326 ${\AA}$ in rms for ZERODUR and fused silica, respectively. To obtain the high reflectivity, 22 thin film layers of $SiO_2$ and $Ta_2O_5$ were deposited by Ion Beam Sputtering. The measured light scattering of ZERODUR and fused silica mirror were 30.9 ppm and 4.6 ppm, respectively. This shows that the substrate surface roughness is not the only parameter which determines the light scattering of the mirror. In order to investigate the mechanism for additional light scattering of the ZERODUR mirror, the surface roughness of the mirror was measured by AFM and was found to be 2.3 times higher than that of the fused silica mirror. It is believed that there is some mismatch at the interface between the substrate and the first thin film layer which leads to the increased mirror surface roughness. To clarify this, the contact angle measurements were performed by SEO 300A, based on the Giriflaco-Good-Fowkes-Young method. The fused silica substrates with 0.46 ${\AA}$ in its physical surface roughness shows lower contact angle than that of the ZERODUR substrate with 0.31 ${\AA}$. This indicates that the thin film surface roughness is determined by not only its surface roughness but also the surface energy of the substrate, which depends on the chemical composition or crystalline orientation of the materials. The surface energy of each substrate was calculated from a contact angle measurement, and it shows that the higher the surface energy of the substrate, the better the surface roughness of the thin film.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Korean Recycled Construction Resources Institute
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• v.4 no.4
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• pp.388-395
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• 2016

This paper explores the photocatalytic sensitivity of cement mortar incorporated with recycled $TiO_2$ from waste water sludge. Basically, $TiO_2$ cluster sank down slowly to the bottom of cement mortar specimen before setting and hardening process. This leads the mismatch of $TiO_2$ concentration on the top and the bottom faces of a specimen. This poorly dispersed $TiO_2$-cement mortar naturally exhibits poor NOx removal efficiency especially on the top of cementitious structure. In architectural engineering application such as building or housing structures, one can simply filp over from the bottom so that more $TiO_2$ concentrated surface can be placed outward into the air. However, in highway pavement case, this could not be applicable due to in-situ installation of concrete pavement. Hence, the dispersion of $TiO_2$ cluster inside the cementitous material is getting important issue onto road construction application. To elaborate this issue, according to our results, silica fume, high-ranged water reducer, viscosity agent, blast furnace slag were not enhanced much of dispersion characteristics of $TiO_2$ cluster. The combination of foaming agent and accelerator of hardening with viscosity agent and small grain size of fine aggregate may help the dispersion of $TiO_2$ inside cementitious materials. Even though the enhanced dispersion were applied to the specimen, NOx removal efficiency doest not change much for the top surface of the specimen. This concurrently affected by the presence of tiny air voids and the dispersion of $TiO_2$ in that these voids could easily adsorbed NOx gas with the aid of large surface area.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Korean Institute of Landscape Architecture
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• v.42 no.6
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• pp.101-110
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• 2014

This study analyzes the validity of the type classification of the type and design changes of apartment landscaping planting construction design changes that were completed in the private sector, efficiently manages the design changes that are displayed over landscaping planting work in general in the future, and performs research by placing the object underlying the presentation. The results are as follows. First, the percentage that occurred in the planting construction of design changes that have occurred in the apartment landscaping construction was carried out in the private sector and accounted for 61.8%. This indicates that part of the planting is a major design change. Second, as the cause of such a design change to be those associated with the field conditions such as lack of main construction period. In particular, due to a change in oral, appeared 7-48 times design changes of one review design change approval is complex, design changes of planting construction had shown a feature that occurs in multiple simultaneous. Third, the 7 types of Design Changes in planting design were delineated as 'design changes for consideration of the user', 'design changes for image improvement', 'design changes for ease of maintenance', 'design changes due to the mismatch of design statement', 'design changes due to the relationship with the engineering species of other', 'design changes due to lack of field study', and 'design changes due to the consideration of feasibility.' Fourth, 'design changes for consideration of the user' and 'design changes for image improvement' were found in more than half of the frequency of the overall changes. This differed from the results shown in public corporations. Fifth, if planting construction design change process, private companies, it was found that is showing the approval of the practice after the previous construction of the construction cost savings due to construction time. However, in the case of a public corporation, these exhibited a different aspect from the private sector and show a design change procedure that reflects the changes after the design change events in the field have occurred. The above results, the type of landscaping works in planting design change of public enterprises, regardless of the private sector, is the same in the seven types, the main reason of and procedures for design changes, indicating that there are other respects. In design change, it may be desirable to apply becomes liquidity rationality and efficiency of the dimension, depending on the nature of the landscape construction.