• 한국자기학회:학술대회 개요집
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• 한국자기학회 2000년도 International Symposium on Magnetics The 2000 Fall Conference
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• pp.5-32
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• 2000

MRAM, High performance MRAM using MTJS demostrated, fully integrated MTJ MRAM with CMOS circuits, write time ~2.3 nsec; read time ~3 nsec, Thermally stable up to ~350 C, Switching field distibution controlled by size & shape. Magnetic Tunnel Junction Properties, Magnetoresistance: ~50% at room temperature, enhanced by thermal treatment, Negative and Positive MR by interface modification, Spin Polarization: >55% at 0.25K, Insensitive ot FM composition, Resistance $\times$ Area product, ranging from ~20 to 10$^{9}$ $\Omega$(${\mu}{\textrm}{m}$)$^{2}$, Spin valve transistor, Tunnel injected spin polarization for "hot" electrons, Decrease of MTJMR at high bias originates from anode.

• 한국전자통신학회논문지
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• 제7권4호
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• pp.833-837
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• 2012

SC1(Standard Cleaning) 시간을 줄여 STI 측벽에서의 실리콘 손실 및 과도절개를 최소화하여 DRAM에서의 데이터 유지시간을 증가시키는 방법을 제안한다. SC1 시간 최적화를 통해 STI 상층 모서리부에서의 기생 전기장을 약화시킴으로서 Inverse Narrow Width 효과를 감소시키면 셀 트랜지스터의 Subthreshold 누설의 증가없이 채널 도핑농도가 감소하게 된다. 이것은 셀 접합에서 P-Well간 공핍 영역에서의 전기장을 최소화하여 일드나 데이터 유지시간의 증가를 보여 주었다.

• 한국재료학회지
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• 제26권11호
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• pp.635-643
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• 2016

Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

• 한국물환경학회지
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• 제23권6호
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• pp.889-896
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• 2007

From the direct outflow of Chungju Dam to the junction of water body and watershed in Paldang lake is the scope of this research. This study performed to investigate the main cause of water quality deterioration and the influenced region in the middle field range of the Namhan river Basin with the onsite measurement of water quality and flow rate simultaneously during spring dry season. The purpose of this study is to find out the time-spatial variation characteristics of water quality and flow rate. Following the flow direction $BOD_5$ and $COD_{Mn}$ concentration increased to the highest value of 3.7 mg/L, 5.9 mg/L at Wolgesa respectively. Chl.a concentration increased to $50mg/m^3$ or so at Kangsang, after that it decreased to $37mg/m^3$ at the junction of Paldang lake. Organic matter concentration variation trend showed similar than that of Chl.a. Also $BOD_5$ concentration tendency was similar to Chl.a in every measuring sites except Paldang lake mixing zone. The major factors of water quality deterioration in Namhan river and Paldang lake during dry season were algal bloom and followed internal production. High phosphorus load from Dalcheon and Seom river caused dry season algal bloom and internal production in transitional zone which was stagnant area in downstream of Namhan river.

• 한국진공학회지
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• 제14권4호
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• pp.229-237
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• 2005

바이어스 스트레스 인가 후에 발생하는 실리콘-게르마늄 이종접합 바이폴라 트랜지스터(SiGe HBT)의 열화현상을 고찰하였다. SiGe HBT가 바이어스 스트레스에 일정 시간 노출되면 소자 내부의 변화에 의하여 소자 파라미터가 원래 값으로부터 벗어나게 된다. 에미터-베이스 접합에 역방향 바이어스 스트레스가 걸리면 전기장에 의해 가속된 캐리어가 재결합 중심을 생성하여 베이스 전류가 증가하고 전류이득이 감소한다. $140^{\circ}C$ 이상의 온도에서 높은 에미터 전류를 흘려주는 순방향 바이어스 전류 스트레스가 가해지면 Auger recombination이나 avalancHe multiplication에 의해 형성된 핫 캐리어가 전류이득의 변동을 유발한다. 높은 에미터 전류와 콜렉터-베이스 전압이 동시에 인가되는 mixed-mode 스트레스가 가해지면 에미터-베이스 역방향 바이어스 스트레스의 경우와 마찬가지로 베이스 전류가 증가한다. 그러나 miked-mode 스트레스 인가 후에는 inverse mode Gummel 곡선에서 베이스 전류 증가가 관찰되고 perimeter-to-area(P/A) 비가 작은 소자가 심각하게 열화되는 등 에미터-베이스 역방향 바이어스 스트레스와는 근본적으로 다른 신뢰성 저하 양상이 나타난다.

• 한국의학물리학회지:의학물리
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• 제12권2호
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• pp.161-169
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• 2001

두경부 종양의 방사선치료에서 비대칭 콜리메이터를 이용한 이분조사는 두 조사면을 겹침없이 연결시켜 조사할 수 있는 효과적인 방법이고, 동일 방사선 조사면을 분리하여 X-선과 전자선을 인접시켜 조사하는 경우는 빈번히 사용되는 방법이다. 본 연구는 X-선의 이분조사면을 이용한 두 조사면의 인접면의 선량과, X-선과 전자선 조사면의 인접면에서 선량을 측정하여 임상에 적용할 수 있는 자료를 얻고자 하였다. X-선의 반쪽 조사면의 선량측정에서 하부 전방 단일 이분조사면의 선량분포는 Y축이 0 cm인 면(콜리메이터가 닫힌 면)에서 0.5 cm, 1 cm 거리에서는 각각 개방조사 선량의 93%, 95%, 전후방 이분조사의 경우 Y축이 0 cm인 면에서 0.3 cm, 0.5 cm, 1 cm거리에서는 각각 개방조사 선량의 92%, 95%, 98%로 선량감소를 보였다. X-선과 전자선의 조사면을 인접시켰을 때 깊이 0 cm, 0.5 cm, 1.5 cm, 2 cm, 3 cm에서의 두 조사면의 인접면에서의 선량 분포의 분석에서 X-선 조사면에서 선량 증가는 깊이 1.5 cm에서 폭 7 mm에 걸쳐 있었고 최고 6%의 증가를 보였으며 다른 측정 깊이에서는 선량증가가 허용범위 내에 있었다. 그리고 전자선 조사면쪽에서 선랑 감소는 전 측정 깊이 0.5 cm-3 cm에서 각각 폭이 1mm-12.5 mm에 걸쳐 4.5%- 30%의 주변부 보다 선량감소를 보였다. 본 연구에서 이분 조사면의 선량은 콜리메이터가 닫힌 면에서 감소함을 확인하였다. 그리고 X-선과 전자선을 인접시켜 조사 할 때 두 조사면의 인접면을 중심으로 X-선 조사면 쪽에서 선량증가, 전자선 조사면쪽에서 선량 감소를 보임을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.247-252
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• 2012

IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.213-217
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• 2015

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.