• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1308-1313
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• 2004

Proton irradiation technology was used for the improvement of power diode switching characteristics. Proton irradiation was carried out at the energies of 2.32 MeV, 2.55 MeV, 2.97 MeV so that the projection range of irradiated proton would be at the metallurgical junction, depletion region and neutral region of pn diode, respectively. Dose conditions were varied into three conditions of 1${\times}$10$^{11}$ cm$^{-2}$ , 1${\times}$10$^{12}$ cm$^{-2}$ , 1${\times}$10$^{13}$ cm$^{-2}$ at each condition of energies. Characterization of the device was performed by I-V(current-voltage), C-V(capacitance-voltage) and trr(reverse recovery time) measurement. At the optimum condition of irradiation, the reverse recovery time of device has been reduced about 1/5 compared to that of original un-irradiated device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.247-252
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• 2012

IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.51-56
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• 1999

This paper presents a new transient overvoltage blocking device (TOBD) for info-communication facilities with low power and high frequency bandwidth. Conventional protection devices have some problems such as low frequency bandwidth, low energy capacity and high remnant voltage. In order to improve these limitations, thehybrid type TOBD, which consists of a gas tube, avalanche diodes and junction typefield effect transistors (JFETs), was designed and fabricated. The TOBD differs from the conventional protection devices in configuration, and JFETs were used as an active non-linear element and a high speed switching diode with low capacitance limits high current. Therefore the avalanche dilde with low energy capacity are protected fromthe high current, and the TOBD has a very small input capacitance. From the performance test using combination surge generator, which can produce $1.2/50\mus\;4.2kV_{max}\; 8/20\mus\; 2.1kA_{max}$, it is confirmed that proposed TOBD has an excellent protection performance in tight clamping voltage and limiting current characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.912-916
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• 2001

Fluxmeter is a measuring instrument the magnetic flux intensity by means of an integration of the voltage induced to a search coil to unit time. It also is required to a precise integrator since the voltage induced to a search coil has a differential value of the flux ${\Phi}$ to unit time. In this study, a bias current which is a main problem of the integrator in a drift troublesome depending on the temperature of a FET is investigated. We have confirmed that the temperature dependence of both the bias current of a integrator using the FET and the reversal saturated current of the minor carrier in a P-N junction of a semiconductor were the same. The property of a commercial integrator goes rapidly down with increasing temperature. The bias current of a FET is increased twice as much with 10$^{\circ}C$ increment. As a result, the low drift integrator could be developed by setting the lower temperature up with a pottier device.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.18-24
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• 2012

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.160-160
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• 2016

In this study, we applied the low temperature curing Ag paste to replace PVD System. The electrode formation of low temperature curing Ag paste for silicon Hetero-junction solar cells is important for improving device characteristics such as adhesion, contact resistance, fill factor and conversion efficiency. The low temperature curing Ag paste is composed various additives such as solvent, various organic materials, polymer, and binder. it depends on the curing temperature conditions. The adhesion of the low temperature curing Ag paste was decided by scratch test. The specific contact resistance was measured using the transmission line method. All of the Ag electrodes were experimented at various curing temperatures within the temperature range of $160^{\circ}C-240^{\circ}C$, at $20^{\circ}C$ intervals. The curing time was also changed by varying the conditions of 10-50min. In the optimum curing temperature $200^{\circ}C$ and for 20 min, the measured contact resistance is $19.61m{\Omega}cm^2$. Over temperature $240^{\circ}C$, confirmed bad contact characteristic. We obtained photovoltaic parameter of the industrial size such as Fill Factor (FF), current density (Jsc), open-circuit voltage (Voc) and convert efficiency of up to 76.2%, 38.1 mA/cm2, 646 mV and 18.3%, respectively.

• Journal of Korean Neurosurgical Society
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• v.48 no.1
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• pp.46-52
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• 2010

Objective : In cervico-thoracic junction (CTJ), the use of strong fixation device such as pedicle screw-rod system is often required. Purpose of this study is to analyze the anatomical features of C7 and T1 pedicles related to screw insertion and to evaluate the safety of pedicle screw insertion at these levels. Methods : Nineteen patients underwent posterior CTJ fixation with C7 and/or T1 included in fixation levels. Seventeen patients had tumorous conditions and two with post-laminectomy kyphosis. The anatomical features were analyzed for C7 and T1 pedicles in 19 patients using computerized tomography (CT). Pedicle screw and rod fixation system was used in 16 patients. Pedicle violation by screws was evaluated with postoperative CT scan. Results : The mean values of the width, height, stable depth, safety angle, transverse angle, and sagittal angle of C7 pedicles were $6.9{\pm}1.34\;mm$, $8.23{\pm}1.18\;mm$, $30.93{\pm}4.65\;mm$, $26.42{\pm}7.91$ degrees, $25.9{\pm}4.83$ degrees, and $10.6{\pm}3.39$ degrees. At T1 pedicles, anatomic parameters were similar to those of C7. The pedicle violation revealed that 64.1% showed grade I violation and 35.9% showed grade II violation, overall. As for C7 pedicle screw insertion, grade I was 61.5% and grade II 38.5%. At T1 level, grade I was 65.0% and grade II 35.0%. There was no significant difference in violation rate between the whole group, C7, and T1 group. Conclusion : C7 pedicles can withstand pedicle screw insertion. C7 pedicle and T1 pedicle are anatomically very similar. With the use of adequate fluoroscopic oblique view, pedicle screw can be safely inserted at C7 and T1 levels.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.