• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• Journal of information and communication convergence engineering
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• v.1 no.3
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• pp.139-142
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• 2003

In this paper, we consider the factors that affect a conversion loss performance in designing a single balanced diode mixer integrated with IRF(Image Reject Filter), based on the embedded electrical wavelength placed between the IRF and mixer, diode matching and LO drive amplifier. To evaluate the conversion loss performance, we suggest two types of a single balanced mixer using 90 degree branch line coupler, microstrip line and schottky diode. One is only mixer and the other is integrated with IRF and LO drive amplifier. The measured results of a single balance diode mixer integrated IRF show the conversion loss of 8.5 dB and the flatness of 1 dB p-p from 21.2 GHz to 22.6 GHz with 10 dBm LO. The measured input PI dB and IIP3 are 7 dBm and 15 dBm respectively under the nominal LO power level of 10dBm. The LO/RF and LO/IF isolation are 22 dB and 50 dB, respectively.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.1-7
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• 1997

In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.7-18
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• 2002

Single-ended differential RF circuit topologies fully utilizing complementary characteristics of both NMOS and PMOS are proposed, which have inherent advantage of both single-ended and differential circuits. Using this concept, we propose a CCPP (Complementary CMOS parallel push-pull) amplifier which has single-ended input/output with differential amplifying characteristics, leading to more than 30 dB improvement on $IIP_2$. In addition, complementary resistive mixer is also proposed, which provides not only differential IF outputs from single-ended RF input, but much better linearity as well as isolation characteristics. Experimental results using $0.35{\;}\mu\textrm{m}$ CMOS process show that, compared with conventional NMOS resistive mixer, the proposed mixer shows 15 dB better LO-to-IF isolation, 4.6 dB better $IIP_2$, and 4.5 dB better $IIP_3$performances.

• Journal of Advanced Navigation Technology
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• v.16 no.3
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• pp.433-439
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• 2012

In this paper, we proposed the triplexer using unit-cell of CRLH transmission line which has a bandpass characteristic to reduce adjacent channel interference. The input impedance of triplexer with each channel filter is operated open-circuit at the resonance frequencies of other channels. Such property is due to the combination a series and parallel resonance circuits of CRLH-TL unit-cell. The measured triplexer results are showed a measured insertion loss of each channel, less than 1.5 dB, matching at each port, less than 15dB and isolation between channel, better than 25 dB. Also, to validate the triplexer, a small signal amplifier with triple-band is designed and tested. the measured amplifier results show good agreements with prediction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.106-113
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• 2003

In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.787-790
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• 2003

A 4-wavelength optical transceiver system is designed and implemented by using 4 OADMs (optical add-drop multiplexers), WDMs, and optical transceivers. In this new system, the wavelengths of 1510 nm and 1530 nm are used for upload and download signals, respectively, as well as the wavelengths of 1550 nm and 1310 nm which have been utilized in a 2-wavelength optical transceiver systems. The 4-wavelength optical module shows very encouraging pass characteristics of about - 5 dB and isolation characteristics of less than -40 dB, which is configured with two OADMs, 4 couplers, and WDM couplers by fusion splicing. Noise figure (NF) of the one-stage balanced amplifier designed and fabricated for receiver module is 0.38 dB and the amplifying gain is 14.2 dB. S$_{11}$, S$_{22}$ and input, output VSWR are -28.81 dB, -32.08 dB, 1.05 : 1, 1.08 : 1, respectively.y.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.