• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.644-651
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• 2007

In multiple antenna systems, vertical Bell Labs Layered Space-Time (V-BLAST) systems enable very high throughput by nulling and cancelling at each layer detection. In this paper, we propose a V-BLAST system which combines with signal space diversity technique. The benefit of the signal space diversity is that we can obtain an additional gain without extra bandwidth and power expansion by applying inphase/quadrature interleaving and the constellation rotation. Through simulation results, it is shown that the performance of the proposed system is less than 0.5dB away from the ideal upper bound.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.198-200
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• 2018

In this paper a single-stage single-phase differential type isolated AC-DC converter is proposed. This converter eliminates the requirement to use bulky electrolytic capacitor from the system and at the same time provides DC charging by employing the AC Power Decoupling waveform control method. All the switches of the converter achieve ZVS turn on during half line cycle and all diodes achieve ZCS turn off during entire line cycle. A conventional controller is implemented for PFC control and output regulation, whereas a power decoupling controller is added to compensate $2^{nd}$ harmonic ripple power. In addition, an interleaving technique is applied to increase the power range of the converter and reduce the input inductor size. In the end simulation verification is performed and results are obtained for 6.6KW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.485-497
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• 2009

In this paper, we described DVB-S2 system for mobility. cross layer coding technique are needed to maintain the performance in deep fading channel. Cross layer coding is divided into two kinds of level. First level is Physical layer coding and, second layer is link layer or upper layer coding. Fixed on DVB-S2 short frame coding method as a physical layer, we simulated the various coding method as an upper layer coding. Furthermore, we analyzed the performance of each coding method on according to mobile vehicle speed, data rate, interleaving memory size, and IP packet size.

• Journal of IKEEE
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• v.26 no.3
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• pp.506-509
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• 2022

In a secret sharing scheme, secret information must be distributed and stored to users, and confidentiality must be able to be reconstructed only from an authorized subset of users. To do this, secret information among different code words must not be subordinate to each other. The minimal code is a kind of linear block code to distribute these secret information not mutually dependent. In this paper, we present a novel extension technique for minimal codes. The product of an arbitrary vector and a minimal code produces a new minimal code with an extended length and Hamming weight. Accordingly, it is possible to provide minimal codes with parameters not known in the literature.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.595-602
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• 2003

This Paper presents an efficient hybrid techniques for a standard cell placement. The prototype tool adopts a middle-down methodology in which an n${\times}$m grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework [12］in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search“move.”Details of this approach including a novel placement legalization procedure are presented. When a global placement converges, a detailed placement is formed and further optimized by the optimal interleaving technique[13］. Experimental results on MCNC benchmarking circuits are presented and compared with the Feng Shui's results in［14］. Solution Qualifies are almost the same as the Feng Shui's results.

• Journal of KIISE:Software and Applications
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• v.27 no.2
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• pp.108-119
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• 2000

Most of prior works on testing parallel programs have concentrated on how to guarantee the reproducibility by employing event traces exercised during executions of a program. Consequently, little work has been done to generate meaningful event sequences, especially, from specifications. This paper describes techniques for deriving event sequences from Message Sequence Charts(MSCs) which are widely used in telecommunication areas for its simplicity in specifying the behaviors of a program. For deriving event sequences from MSCs, we have to uncover the causality relations among events embedded implicitly in MSCs. In order to attain this goal, we adapt vector time stamping which has been previously used to determine the ordering of events taken place during an execution of interacting processes. Then, valid event sequences, satisfying the causality relations, are generated according to the interleaving rules suggested in this paper. The feasibility of our testing technique was investigated using the phone conversation example. In addition, we discussed on the experimental results gained from the example and how to combine various test criteria into our testing environment.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1031-1038
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• 2005

In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.