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Hybrid Techniques for Standard Cell Placement  

허성우 (동아대학교 전기전자컴퓨터공학부)
오은경 (동아대학교 컴퓨터공학과)
Abstract
This Paper presents an efficient hybrid techniques for a standard cell placement. The prototype tool adopts a middle-down methodology in which an n${\times}$m grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework [12]in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search“move.”Details of this approach including a novel placement legalization procedure are presented. When a global placement converges, a detailed placement is formed and further optimized by the optimal interleaving technique[13]. Experimental results on MCNC benchmarking circuits are presented and compared with the Feng Shui's results in[14]. Solution Qualifies are almost the same as the Feng Shui's results.
Keywords
VLSI layout; standard cell; placement;
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Times Cited By KSCI : 1  (Citation Analysis)
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[ GSRC ] / Bookshelf slot
2 Reporting of Standard Cell Placement Results /
[ Patrick H. Madden ] / IEEE Trans. of CAD
3 M. Wang and M. Sarrafzadeh, 'Behavior of Congestion Minimization During Placement,' in Proc. of International Symposium on Physical Design, pp. 145-150, 1999   DOI
4 C. Sechen and K. W. Lee, 'An Improved Simulated Annealing Algorithm for Row-Based Placement,' in Proc. of IEEE International Conference on Coumputer-Aided Design, pp. 478-481, 1987
5 M. A. Breuer, 'Min-cut Placement,' Design Automation and Fault-Tolerant Computing, pp. 343-382, 1977
6 D. J. H. Huang and Andrew B. Kahng, 'Partitioning-Based Standard-Cell Global Placement with an Exact Objective,' in Proc. of International Symposium on Physical Design, pp. 18-25, 1997   DOI
7 C. M. Fiduccia and R. M. Mattheyses, 'A Linear Time Heuristic for Improving Network Partitions,' in Proc. of ACM/IEEE Design Automation Conference, pp. 175-181, 1982
8 Wern-Jieh Sun and Carl Sechen, 'Efficient and Effective Placement for Very Large Circuits,' IEEE Transactions on Computer-Aided Design, pp. 349-359, 1995   DOI   ScienceOn
9 Sivanarayana Mallela and Lov K. Grover, 'Clustering Based Simulated Annealing for Standard Cell Placement,' in Proc. of Design Automation Conference, pp. 312-317, 1988   DOI
10 Majid Sarrafzadeh and Maogang Wang, 'NRG:Global and Detailed Placement,' in Proc. of IEEE International Conference on Coumputer-Aided Design, pp. 532-537, 1997   DOI
11 G. Sigl, K. Doll and F Johannes, 'Anylytical Placement: A Linear or a Quadratic Objective Function?,' in Proc. of ACM/IEEE Design Automation Conference, pp. 427-432, 1991
12 H. Eisenmann and F. M. Johannes, 'Generic Global Placement and Floorplanning,' in Proc. of ACM/IEEE Design Automation Conference, pp. 296-274, 1998   DOI
13 Patrick H. Madden, 'Reporting of Standard Cell Placement Results,' IEEE Trans. of CAD, pp. 240-247, 2002   DOI   ScienceOn
14 A. E. Caldwell, A. B. Kahng and I. L. Markov, 'Optimal End-Case Partitioners and Placers for Standard-Cell Layout,' in Proc. of International Symposium on Physical Design, pp. 90-96, 1999   DOI
15 Sung-Woo Hur and John Lillis, 'Relaxation and Clustering in a Local Search Framework: Application to Linear Placement,' VLSI Design, Vol. 14, No. 2, pp. 143-154, 2002   DOI
16 오은경, 허성우, '동적 프로그래밍 기법을 이용한 효율적인 배치 개선 알고리즘,' 한국정보처리학회 추계학술발표대회, 2002   과학기술학회마을
17 GSRC Bookshelf slot [online] 'http://www.gagascale.org/bookshelf.'