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Hardware Implementation of FPGA-based Real-Time Formatter for 3D Display  

Seo Young-Ho (한성대학교 정보통신공학과)
Kim Dong-Wook (광운대학교 전자제료공학과 디지털 설계 및 테스트 연구실)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.9, no.5, 2005 , pp. 1031-1038 More about this Journal
Abstract
In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.
Keywords
3D display; formatter; FPGA; LCD;
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