• 한국표면공학회지
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• 제46권2호
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• pp.68-74
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• 2013

For the coating of diamond films on WC-Co tools, a buffer interlayer is needed because Co catalyzes diamond into graphite. W and Ti were chosen as candidate interlayer materials to prevent the diffusion of Co during diamond deposition. W or Ti interlayer of $1{\mu}m$ thickness was deposited on WC-Co substrate under Ar in a DC magnetron sputter. After seeding treatment of the interlayer-deposited specimens in an ultrasonic bath containing nanometer diamond powders, $2{\mu}m$ thick nanocrystalline diamond (NCD) films were deposited at $600^{\circ}C$ over the metal layers in a 2.45 GHz microwave plasma CVD system. The cross-sectional morphology of films was observed by FESEM. X-ray diffraction and visual Raman spectroscopy were used to confirm the NCD crystal structure. Micro hardness was measured by nano-indenter. The coefficient of friction (COF) was measured by tribology test using ball on disk method. After tribology test, wear tracks were examined by optical microscope and alpha step profiler. Rockwell C indentation test was performed to characterize the adhesion between films and substrate. Ti and W were found good interlayer materials to act as Co diffusion barriers and diamond nucleation layers. The COFs on NCD films with W or Ti interlayer were measured as less than 0.1 whereas that on bare WC-Co was 0.6~1.0. However, W interlayer exhibited better results than Ti in terms of the adhesion to WC-Co substrate and to NCD film. This result is believed to be due to smaller difference in the coefficients of thermal expansion of the related films in the case of W interlayer than Ti one. By varying the thickness of W interlayer as 1, 2, and $4{\mu}m$ with a fixed $2{\mu}m$ thick NCD film, no difference in COF and wear behavior but a significant change in adhesion was observed. It was shown that the thicker the interlayer, the stronger the adhesion. It is suggested that thicker W interlayer is more effective in relieving the residual stress of NCD film during cooling after deposition and results in stronger adhesion.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.144-147
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• 2003

Cu+ ions drift diffusion in formal oxide film and SiOCH film for interlayer dielectric is evaluated. The diffusion is investigated by measuring shift in the flatband voltage of capacitance/voltage measurements on Cu gate capacitors after bias temperature stressing. At a field of 0.2MV/cm and temperature $200^{\circ}C,\;300^{\circ}C,\;400^{\circ}C,\;500^{\circ}C$ for 10min, 30min, 60min. The Cu+ ions drift rate of $SiOCH(k=2.85{\pm}0.03)$ film is considerable lower than termal oxide. As a result of the experiment, SiOCH film is higher than Thermal oxide film for Cu+ drift diffusion resistance. The important conclusion is that SiOCH film will solve a causing reliability problems aganist Cu+ drift diffuion in dielectric materials.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2013년도 추계학술대회 논문집
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• pp.501-505
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• 2013

It is well known that monolithic glass has specific coincidence dip allowing transmittance of noise around the critical frequency. Laminated glass, made of a polyvinyle butyral(PVB) interlayer sandwiched by two panes of glass sheet, has long served for the advantage in noise attenuation properties as well as the safety purpose. More research on the improvement of sound insulation performance is needed, considering much of the noise is still transmitted through the glass. As a preliminary study, authors have made several test specimens, varied combinations of glass and interlayer film, to optimize the acoustic performance. Experimental investigation was carried out to study the sound transmission loss of test specimens in the reverberation chamber by using sound intensity method. Several new applications, instead of the existing PVB laminated glass, show better results in sound transmission loss and low temperature have a bad influence on the acoustic performance.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• 한국표면공학회지
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• 제51권4호
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• pp.243-248
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• 2018

All solid state thin film batteries with two types of cell structure, Pt / $LiCoO_2$ / LiPON / Cu and Pt / $LiCoO_2$ / LiPON / $LiCoO_2$ / Cu, are prepared and their electrochemical performances are investigated to evaluate the effect of $LiCoO_2$ interlayer at the interface of LiPON / Cu. The crystallinity of the deposited $LiCoO_2$ thin films is confirmed by XRD and Raman analysis. The crystalline $LiCoO_2$ cathode thin film is obtained and $LiCoO_2$ as the interlayer appears to be amorphous. The surface morphology of Cu current collector after cycling of the batteries is observed by AFM. The presence of a 10 nm-thick layer of $LiCoO_2$ at the interface of LiPON / Cu enhances the interfacial adhesion and reduces the interfacial resistance. As a result, Li plating / stripping at the interface of LiPON / Cu during charge/discharge reaction takes place more uniformly on Cu current collector, while without the interlayer of $LiCoO_2$ at the interface of LiPON / Cu, the Li plating / stripping is localized on current collector. The thin film batteries with the interlayer of $LiCoO_2$ at the interface of LiPON / Cu exhibits enhanced initial coulombic efficiency, reversible capacity and cycling stability. The thickness of the anode current collector Cu also appears to be crucial for electrochemical performances of all solid state thin film batteries.

• 열처리공학회지
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• 제5권1호
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• pp.1-12
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• 1992

In order to improve adhesive force of TiN film, we sputtered titanium as interlayer before TiN deposition by Plasma Enhanced Chemical Vapour Deposition. We observed changes of hardness and adhesion at a various thickness of titanium interlayer and also examined analysis. At the critical thickness of the titanium interlayer(about $0.2{\mu}$), adhesive force of TiN films were promoted mostly. But over the critical thickness, a marked reduction of adhesive force was showed, because of the internal stress of titanium interlayer. From AES analysis, the adhesion improvement of TiN films was mainly caused by nitrogen diffusion into titanium interlayer during TiN deposition process which relieved stress concentration at TiN coating-substrate interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1775-1778
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• 2006

Through baking process on an interlayer, known as hole transporting layer, varying baking temperature up to 300 degree, which is considered as extremely high for polymer light emitting device (PLED) system, we found interesting relationship between packing density and morphology affecting device performance. Granular morphology shows that as temperature increases, grain size is getting smaller to pack closely and make interlayer harden. Such denser interlayer has temperature dependency of its own mobility, even without clear evidence of degradation of material itself. Its fact proven in a single film also reflects on multilayered PLED's performance like IVL, efficiency, lifetime. It's found that, especially, to enhance lifetime is related with thermal stability of interlayer and its mobility dependency to meet better charge balance. Therefore, it gives us understanding not only baking effect of interlayer, but also material & device designing guide to enhance lifetime.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2006년도 춘계학술발표회 초록집
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• pp.89-89
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• 2006

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.672-675
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• 1999

Si-to-Si electrostatic bonding was carried out by employing LSG interlayer instead of conventional Corning #7740 interlayer in order to improve bonding properties. The surface roughness and dielectric breakdown field of the LSG interlayers deposited on Si substrates were investigated. Also, the bonding interface, bonding strength and bonding mechanism were discussed for the electrostatically-bonded Si-Si wafer pairs having LSG interlayers.