• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of IKEEE
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• v.25 no.3
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• pp.501-505
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• 2021

In this study, we fabricated amorphous indium-tin-gallium-zinc-oxide thin-film transistors (a-ITGZO TFTs) with gate dielectrics of HfO₂ and the mixed layers of HfO₂ and Al₂O₃, and investigated the effect of gate dielectric on electrical characteristics of a-ITGZO TFTs. When only HfO₂ was used as the gate dielectric, the mobility and subthreshold swing (SS) were 32.3 cm²/Vs and 206 mV/dec. For the a-ITGZO TFTs with gate dielectric made of HfO₂ and Al₂O (2:1, 1:1), the mobilities and SS were 26.4 cm²/Vs (2:1), 16.8 cm²/Vs(1:1), 160 mV/dec (2:1) and 173 mV/dec (1:1). On the other hand, the hysteresis window shown in transfer curves of the a-ITGZO TFTs was lessened from 0.60 to 0.09 V by the increase of Al₂O₃ ratio in gate dielectric, indicating that the interface trap density between the gate dielectric and channel layer decreases due to Al₂O₃.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.18-23
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• 2009

The effect of hydrogen-nitrogen annealing on the interface trap properties of Metal-Oxide-Nitride-Oxide-Silicon (MONOS) capacitors is investigated by analyzing the capacitors' gate leakage current and the interface trap density between the Si and $SiO_2$ layer. MONOS samples annealed at $850^{\circ}C$ for 30 s by rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing eases $N_2$ and 2% hydrogen and 98% nitrogen gas mixture $(N_2-H_2)$ at $450^{\circ}C$ for 30 mins. Among the three samples as-deposited, annealed in $N_2$ and $N_2-H_2$, MONOS sample annealed in an $N_2-H_2$ environment is found to have the lowest increase of interface-trap density from the capacitance-voltage experiments. The leakage current of sample annealed in $N_2-H_2$ is also lower than that of sample annealed in $N_2$.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.46-49
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• 1994

In this paper we investigate the characteristics of switching and memory traps in sealed MONOS nonvolatile memory devices with different nitride thicknesses. We have demonttrated flatband voltage shift of 1V with 5V programming voltage. By fitting the experimental observations with theoretical calculations, trap density and capture cross section of memory trap at the nitride-blocking oxide interface are estimated to be 1.0${\times}$10$\^$13/ cm$\^$-2/ and 8.0${\times}$10$\^$14/ cm$\^$-2/

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.411-414
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• 1999

70 ${\AA}$-thick oxides nitridied at various conditions were reoxidized at pemperatures of 900$^{\circ}C$ in dry-O$_2$ ambients for 5～40 mininutes. The gate oxide interface porperties as well as the oxide substrate interface properties of MOS(Metal Oxide Semiconductor) capacitors with various nitridation conditions, reoxidation conditions and pure oxidation condition were investigated. We stuided I$\sub$g/-V$\sub$g/ characteristics, $\Delta$V$\sub$g/ shift under constant current stress from electrical characteristics point of view and breakdown voltage from leakage current point of view of MOS capacitors with SiO$_2$, NO, RNO dielectrics. Overall, our experimental results show that reoxidized nitrided oxides show inproved charge trapping porperites, I$\sub$g/-V$\sub$g/ characteristics and gate $\Delta$V$\sub$g/ shift. It has also been shown that reoxidized nitridied oxide's leakage currented voltage is better than pure oxide's or nitrided oxide's from leakage current(1${\mu}$A) point of view.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.593-596
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• 1998

Effects of current re-stress after anneal on leakage current and trapped charges in oxides are investigated. Current stress on 6 nm thick oxide has generated mostly positive traps within the oxide resulting in leakage currents. The interface states generated are several orders of magnitude smaller, determined by C-V and charge pumping method. Annealing has eliminated only the charged traps not the neutral traps, thus the leakage current and trap density are increased when the oxides are re-stressed.

• Journal of Sensor Science and Technology
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• v.5 no.6
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• pp.60-67
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• 1996

The interfacial electrical properties of InSb MIS structure with low temperature remote PECVD $SiO_{2}$ have been characterized. The interlace-state density at mid-bandgap of the MIS structure was about $1{\sim}2{\times}10^{11}\;cm^{-2}eV^{-1}$, when the $SiO_{2}$ film was deposited at $105^{\circ}C$. However, large amount of interlace states and trap states were observed in the MIS structure fabricated at temperatures above $105^{\circ}C$. The time constant of $10^{-4}{\sim}10^{-5}\;sec$ of interface states was extracted from G- V measurement. As the deposition temperature increased, the hysteresis of C- V curves were increased due to the high trap density.