Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Interface Traps Analysis as Bonding of The Silicon/Nitrogen/Hydrogen in MONOS Capacitors

실리콘/수소/질소의 결합에 따른 MONOS 커패시터의 계면 특성 연구

  • Kim, Hee-Dong (School of Electrical Engineering, Korea University) ;
  • An, Ho-Myoung (School of Electrical Engineering, Korea University) ;
  • Seo, Yu-Jeong (School of Electrical Engineering, Korea University) ;
  • Zhang, Yong-Jie (School of Electrical Engineering, Korea University) ;
  • Nam, Ki-Hyun (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Chung, Hong-Bay (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Kim, Tae-Geun (School of Electrical Engineering, Korea University)
  • 김희동 (고려대학교 전기전자전파공학과) ;
  • 안호명 (고려대학교 전기전자전파공학과) ;
  • 서유정 (고려대학교 전기전자전파공학과) ;
  • 장영걸 (고려대학교 전기전자전파공학과) ;
  • 남기현 (광운대학교 전자재료공학과) ;
  • 정홍배 (광운대학교 전자재료공학과) ;
  • 김태근 (고려대학교 전기전자전파공학과)
  • Published : 2009.12.25
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Abstract

The effect of hydrogen-nitrogen annealing on the interface trap properties of Metal-Oxide-Nitride-Oxide-Silicon (MONOS) capacitors is investigated by analyzing the capacitors' gate leakage current and the interface trap density between the Si and $SiO_2$ layer. MONOS samples annealed at $850^{\circ}C$ for 30 s by rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing eases $N_2$ and 2% hydrogen and 98% nitrogen gas mixture $(N_2-H_2)$ at $450^{\circ}C$ for 30 mins. Among the three samples as-deposited, annealed in $N_2$ and $N_2-H_2$, MONOS sample annealed in an $N_2-H_2$ environment is found to have the lowest increase of interface-trap density from the capacitance-voltage experiments. The leakage current of sample annealed in $N_2-H_2$ is also lower than that of sample annealed in $N_2$.

본 연구는 실리콘 기판과 실리콘 산화막 사이의 계면 트랩 밀도와 게이트 누설 전류를 조사하여, Metal-Oxide-Nitride-Oxide-Silicon (MONOS) 메모리 소자의 계면 트랩 특성의 수소-질소 열처리 효과를 조사하였다. 고속열처리 방법으로 850도에서 30초 동안 열처리한 MONOS 샘플들을 질소 가스와 수소-질소 혼합 가스를 사용하여 450도에서 30분 동안추가 퍼니스 열처리 공정을 수행하였다. 열처리 하지 않은 것, 질소, 수소-질소로 열처리 한 세 개의 샘플 중에서, 커패시터-전압 측정 결과로부터 수소-질소 열처리 샘플들이 가장 적은 계면 트랩 밀도를 갖는 것을 확인하였다. 또한, 전류-전압 측정 결과에서, 수소-질소 열처리 소자의 누설전류 특성이 개선되었다. 위의 실험 결과로부터, 수소-질소 혼합 가스로 추가 퍼니스 열처리의해 실리콘 기판과 산화막 사이의 계면 트랩 밀도를 상당히 줄일 수 있었다.

Keywords

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