• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.275-279
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• 2004

In this paper, a large-scale, wide-area storage system based on IP is proposed which is under development. OASIS is a storage system enforced with very high-scalability up to hundreds and thousands of clients over IP network, and it is able to extend the service to the wide area network. For this purpose, we adopt an storage interconnection technology based on IP, the object based storage technology and a clustered server architecture which provides high-scalability and availability to our system. This system can be utilized to provide network storage service which gains more reality with the incoming FTTH and WiBro services.

• Journal of Aerospace System Engineering
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• v.1 no.4
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• pp.13-21
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• 2007

As one of YHF digital data link technologies, VDL Mode 2 is designed to be an air-to-ground subnetwork of the Aeronautical Telecommunication Network (ATN) based on the Open System Interconnection (OSI) architecture. VDL Mode 2 can be used in ATS Applications especially for CPDLC and ADS. And it is also expected to replace ACARS (Aircraft Communications Addressing and Reporting System) which has broadly been used in AOC for over 20 years. This paper presents the design result of VDL Mode 2 system under AOA (ACARS Over AVLC) environment for the implementation of bit-oriented ATS applications. The system is composed of airborne and ground subsystem. Airborne subsystem consists of VDR, CMU and an aircraft test equipment with CPDLC/ADS client applications for operational test and ground system consists of Ground Station which includes ground VDR and ground communication controller, simple DSP (Datalink Service Processor) and a ground test equipment with CPDLC/ADS server applications.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.557-562
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• 2005

Throughput and latency of interconnection network are important factors of the performance of multiprocessor systems. The dual-link CC-NUMA architecture using point-to-point unidirectional link is one of the popular structures in high-end commercial systems. In terms of optimal path between nodes, several paths exist with the optimal hop count by its native multi-path structure. Furthermore, transaction latency between nodes is affected by congestion of links on the transaction path. Hence the transaction latency may get worse if the transactions make a hot spot on some links. In this paper, I propose a dynamic transaction routing algorithm that maintains the balanced link utilization with the optimal path length, and I compare the performance with the fixed path method on the dual-link CC-NUMA systems. By the proposed method, the link competition is alleviated by the real-time path selection, and consequently, dynamic transaction algorithm shows a better performance. The program-driven simulation results show $1{\~}10\%$ improved fluctuation of link utilization, $1{\~}3\%$ enhanced acquirement of link, and $1{\~}6\%$ improved system performance.

• Archives of design research
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• v.15 no.4
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• pp.347-358
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• 2002

Architectural drawing has been changing from the general notion, in which it is to predict what it may be like for purely practical purpose. Particularly amongst the Deconstructivists' work, graphic elements make a great contribution to the realization of their self expressive style. Whereas these are often chosen for solely aesthetic reasons, there are some cases in which the act of drawing itself is a crucial, investigative process. This is true of Daniel Libeskind's architectural drawing. For him, Typography seems to be characteristic of his drawing. He Harness typographic elements as metaphors for hid abstract symbolism through his architectural drawings, which retain the possibility to relate to the more radical typographic approaches. Within this context, this thesis will argue how the typographic elements in Daniel Libeskind's architectural drawings can be interpreted. What interconnection can be made between the two practices\ulcorner How can these elements be incorporated into architecture\ulcorner Can they be involved in it as a main constituent\ulcorner This thesis explores diverse possibilities of interpretation of his architectural drawing through typological approaches to the cases where type itself meets the different media and signific ation is given to the other typographic elements.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• Journal of Korean Society of Rural Planning
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• v.16 no.4
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• pp.61-75
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• 2010

Daily living area can be delimited differently depending on what area is to be focused. Based on regional interaction, the present study empirically analyzed the difference between living areas focusing on rural area and ones relying on urban area. We established two types of living areas in Busan-Ulsan mega city with different focus areas (rural versus urban), using travel OD data (2006). According to the result, the fonn of spatial clusters in urban living area differed from that of spatial clusters in rural area; the boundaries of living area were not fit to those of administrative areas in both types; and living areas in both types tended to extend over more than two administrative areas. The results cast some implications concerning spatial planning and policy for living area delimitation. First, since the spatial structure and interconnection of urban area differs to those of rural area, it is required to delimit living areas discriminatively depending on the objectives of the spatial plan. Additionally, the living area should be established more specifically and systematically by further subdividing the form of spaces depending on the objectives and types of the plan. Second, the administrative areas should be consolidated now that the difference of boundaries of administrative and living areas lead to inconvenience of residents, increased administration costs and scale diseconomy. Lastly, the living areas should be delimited by the metropolitan or mega city planning and thus be reflected to its offsprings.

• Journal of Internet Computing and Services
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• v.10 no.5
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• pp.1-12
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• 2009

A routing policy based on BGP community routing permits to select a specific route for particular network by making use of user-defined routing policies. Especially, community based routing policy is recently getting a great concern to enhance overall performance in the global research networks which are generally inter-connected large number of different characterized networks. In this paper, we analyze the community routing which has been applied in existing global research networks in the network performance point of view, and catch hold of problems caused by the routing performance in a new global research network. Then, we suggest an effective community routing policy model along with an interconnection architecture of research networks, in order to make correct some wrong routings and resolve an asymmetric routing problem, for a new global research network. Our work is expected to be utilized as an enabling base technology to improve the network performance of future global research networks as well as commercial networks.