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http://dx.doi.org/10.9708/jksci.2012.17.6.001

Analysis on the Performance and Temperature of the 3D Quad-core Processor according to Cache Organization  

Son, Dong-Oh (School of Electronics and Computer Engineering, Chonnam National University)
Ahn, Jin-Woo (School of Electronics and Computer Engineering, Chonnam National University)
Choi, Hong-Jun (School of Electronics and Computer Engineering, Chonnam National University)
Kim, Jong-Myon (School of Computer Engineering and Information Technology, University of Ulsan)
Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.17, no.6, 2012 , pp. 1-11 More about this Journal
Abstract
As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.
Keywords
Quad-core processor; 3D integrated circuits; Temperature; Cache memory; Mapping method;
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