• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.153-160
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• 1996

In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.6
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• pp.958-965
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• 2002

Current research for software architecture views and models a software system as a set of components and connectors. Components are abstractions of system level computational entities. Connectors are abstractions of components interrelationships. In this paper, we focus on connectors for the JavaBeans-based systems that are built using object integration technologies like CORBA. We present connector model in JavaBeans-based system for object-oriented component integration. We start with a discussion of related work of software architecture research and object-oriented modeling that focuses on the description of component collaborations. We propose connectors as transferable abstractions of system level component interconnection and inter-operation.

• ETRI Journal
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• v.38 no.6
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• Korean Institute of Interior Design Journal
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• v.20 no.4
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• pp.74-82
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• 2011

All the phenomena and subjects of nature and society are within correlation interconnection, and they are inseparably connected one another. The elements of this interaction can be found out through the concept of transparency in the space composition of Korean traditional architecture. This study is focusing on the access space, in other words, a gate-house that is a buffer zone playing a process role up to the main space among successive spaces. It was chosen to be the subject of the study since it strengthens convergence into the main building and with the effect connecting spaces, it could show well the spatial possibility of transparency. Besides, the subject of the study is limited to the Moonru Multi roofs that improves the functionality of spaces between gate-houses, and it is intended to progress contents by comparative analysis of two kinds such as Seo Won gate-house and temple gate-house. Korean traditional architecture places emphasis on harmony within the whole spaces. There are intimate relations between surrounding environment, external spaces and internal spaces, and it is important understand the spatial relations according to the shape appearing through interactions of parts in the whole spaces. In conclusion, the Moonru Multi roofs is analyzed with the method of extracting the concept that is contained in the frame of analysis and through ecological views through a visible and structural method. It can be understood what kinds of method for communication were used for ancestors to recognize and use spaces with the deduced concept through the analysis of the Moonru Multi roofs with different character.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.255-263
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• 2000

A multistage interconnection network is a suitable class of interconnection architecture for constructing large-scale multicomputers. Broadcast and multicast communication are fundamental in supporting collective communication operations such as reduction and barrier synchronization. In this paper, we propose a new multicast technique in wormhole-switched bidirectional multistage banyan networks for constructing large-scale multicomputers. To efficiently support broadcast and multicast with simple additional hardware without deadlock, we propose a two-phase multicast algorithm which takes only two transmissions to perform a broadcast and a multicast to an arbitrary number of desired destinations. We encode a header as a cube and adopt the most upper input link first scheme with periodic priority rotation as arbitration mechanism on contented output links. We coalesce the desired destination addresses into multiple number of cubes. And then, we evaluate the performance of the proposed algorithm by simulation. The proposed two-phase multicast algorithm makes a significant improvement in terms of latency. It is noticeable that the two-phase algorithm keeps broadcast latency as efficient as the multicast latency of fanout 2^m where m is the minimum integer satisfying $2^m{\geq} {\sqrt{N}}$ ( N is a network size).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.257-263
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• 2002

A graph embedding problem has been studied for applications of resource allocation and mapping the underlying data structure of a parallel algorithm into the interconnection architecture of massively parallel processing systems. In this paper, we consider the embedding problem of the pyramid into the regular 2-dimensional mesh interconnection network topology. We propose a new embedding function which can embed the pyramid of height N into 2$^{N}$ x2$^{N}$ 2-dimensional mesh with dilation max{2$^{N1}$-2. [3.2$^{N4}$＋1)/2, 2$^{N3}$＋2. [3.2$^{N4}$＋1)/2]}. This means an improvement in the dilation measure from 2$^{N}$ $^1$in the previous result into about (5/8) . 2$^{N1}$ under the same condition.condition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1180-1192
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• 1996

On demand of many users, basic networks of a parallel computer system are required to have a property that can embed various topologies. Bisectional interconnection network is known to satisfy this property, and it can embed various topologies optimally. Nowadays one is very interested in the hypercube as a message pssing multicomputer system, so it is very important to implement a hypercube in bisectional network. In this paper, a hypercube is implemented in a versatile bisecional netork, and its routing and broadcasting algorithm are proposed. Conventional bisectional network can accomodata linear array, complete binary tree and mesh structure as its topology. Now hypercube is implemented to be utilized as a general purpose supercomputercommunication architecture. The proposed routing and broadcasting algorithm embedded in bisectional network are general purpose algorithms which satisfy property of conventional hypercube.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.68-75
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• 1999

In this paper, we propose a Baysian method estimating system reliability which is more effective and precise than conventional methods using prior information. This technique estimates system reliabilities that an entire system and multiprocessing system is normally working in multiprocessor system and multiple port connected memory architecture. The reason is why internetwork with multiprocessor system is mainly connected as multiple bus structure, crossbar switching structure and multiport connected memory structure.